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WIP: codegen: add B-ASIC commit hash in VHDL preamble

Open Mikael Henriksson requested to merge codegen-commit-hash into master
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@@ -4,6 +4,7 @@ Generation of common VHDL constructs
from datetime import datetime
from io import TextIOWrapper
from subprocess import PIPE, Popen
from typing import Any, Optional, Set, Tuple
from b_asic.codegen.vhdl import VHDL_TAB
@@ -18,9 +19,18 @@ def write_b_asic_vhdl_preamble(f: TextIOWrapper):
f : :class:`io.TextIOWrapper`
The file object to write the header to.
"""
# Try to acquire the current git commit hash
git_commit_id = None
try:
process = Popen(['git', 'rev-parse', '--short', 'HEAD'], stdout=PIPE)
git_commit_id = process.communicate()[0].decode('utf-8').strip()
except:
pass
f.write(f'--\n')
f.write(f'-- This code was automatically generated by the B-ASIC toolbox.\n')
f.write(f'-- Code generation timestamp: ({datetime.now()})\n')
if git_commit_id:
f.write(f'-- B-ASIC short commit hash: {git_commit_id}\n')
f.write(f'-- URL: https://gitlab.liu.se/da/B-ASIC\n')
f.write(f'--\n\n')
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