WIP: codegen: add B-ASIC commit hash in VHDL preamble
Compare changes
Conflict: This file was modified in both the source and target branches.
Ask someone with write access to resolve it.
+ 10
− 0
@@ -4,6 +4,7 @@ Generation of common VHDL constructs
@@ -18,9 +19,18 @@ def write_b_asic_vhdl_preamble(f: TextIOWrapper):