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Mikael Henriksson
Aardvark Design Sweep
Commits
6ace4282
Commit
6ace4282
authored
4 years ago
by
Mikael Henriksson
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Fixed reliability problem with absolute paths.
parent
13cef078
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.sweep.bash.swp
+0
-0
0 additions, 0 deletions
.sweep.bash.swp
run_synth.sh
+1
-1
1 addition, 1 deletion
run_synth.sh
sweep.bash
+16
-2
16 additions, 2 deletions
sweep.bash
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17 additions
and
3 deletions
.sweep.bash.swp
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6ace4282
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run_synth.sh
+
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−
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6ace4282
...
...
@@ -18,4 +18,4 @@ cd $1
name
=
$(
echo
$1
|
sed
's|.*[0-9]\{2\}:[0-9]\{2\}:[0-9]\{2\}/\(.*\)|\1|'
)
printf
" Starting systhesis (
$(
date
+%H:%M:%S
)
): '
$name
'
\n
"
dc_shell-t
-f
sim.tcl 1>
/dev/null
dc_shell-t
-f
sim.tcl 1>
log.txt 2>&1
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sweep.bash
+
16
−
2
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6ace4282
...
...
@@ -5,6 +5,9 @@
# both clock constraints and VHDL design generics. The tool is used by setting
# the global sweeping settings, found just bellow this note, and the results are
# put in a newly created directory named 'sweep_<design_name>_<date_of_sweep>'.
# Any library settings etc that is to be shared among sweeps are to be put in
# the local configuration file '.synopsys_dc.setup' which is sourced by all
# instances of Design Compiler.
# Use the script at your own risk or whatever...
#
# Author: Mikael Henriksson
...
...
@@ -57,7 +60,7 @@ if [ "${#DESIGN_FILES[@]}" -lt 1 ]; then
echo
"Error: No design files (DESIGN_FILES) provided."
&&
exit
-1
fi
for
file
in
"
${
DESIGN_FILES
[@]
}
"
;
do
if
!
[
-f
"
$file
"
]
;
then
if
[
-f
"
$file
"
]
;
then
echo
"Error: Could not locate design file '
$file
'."
&&
exit
-1
fi
done
...
...
@@ -79,6 +82,12 @@ TOP_DIR="sweep_${DESIGN_NAME}_${SCRIPT_LAUNCH_DATE}"
echo
"Creating top directory:
$TOP_DIR
"
mkdir
"
$TOP_DIR
"
||
"Error: failed to create top directory."
||
exit
-1
# Get the absolute path of the design file, which is necessary for the sweep.
DESIGN_FILES_ABSOLUTE
=()
for
file
in
"
${
DESIGN_FILES
[@]
}
"
;
do
DESIGN_FILES_ABSOLUTE+
=(
"
$(
realpath
$file
)
"
)
done
# Initialize designs. We create one sub directory from each design that is
# to be sweept. One design is one design file with one generic setting. Further
# we substitue design options into 'template.tcl' and copy the resulting
...
...
@@ -94,13 +103,18 @@ for design_generics in "${GENERICS[@]}"; do
# Generate synthesis script from template.
cat
"template.tcl"
|
\
sed
"s#__HDL_FILES__#
${
DESIGN_FILES
[@]
}
#"
|
\
sed
"s#__HDL_FILES__#
${
DESIGN_FILES
_ABSOLUTE
[@]
}
#"
|
\
sed
"s/__PERIOD__/
$period
/"
|
\
sed
"s/__CLK_NAME__/
$CLOCK_NAME
/"
|
\
sed
"s/__DESIGN_GENERICS__/
$design_generics
/"
|
\
sed
"s/__DESIGN_NAME__/
$DESIGN_NAME
/"
>
\
"
$sub_dir
/sim.tcl"
# Possibly copy the Design Compiler local setup file.
if
[
-f
".synopsys_dc.setup"
]
;
then
cp
".synopsys_dc.setup"
$sub_dir
/
fi
# Append new synthesis directory to sweep list.
SYNTH_DIRS
=
"
$sub_dir
|
$SYNTH_DIRS
"
done
...
...
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