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Computer Engineering
B-ASIC - Better ASIC Toolbox
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a27da81d863ffa45f483250b4a5872108b37256b
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Branches
20
13-add-coupled-operations-to-sfg
14-coupling-sfg-s
17-operation-replacement-in-a-sfg
2-operation-id-system
22-deep-copy-of-sfg
23-create-custom-operation
31-print-schedule
34-processor-and-memory-information-in-schedules
65-implement-a-workspace-in-the-gui-2
66-load-save-sfg-to-file
82-explode-sfg
84-unfolding-of-an-sfg
87-resize-gui-window
MultiSimPlot
add-fft-generator
add-memory-constraint-for-list-schedulers
add-slack-time-sched
aptcache
codegen-commit-hash
commutative
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2
cbasedsim
1.0.0
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Created with Raphaël 2.2.0
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Remove Input and Output argument to SFG generators
Fixes
Add two examples
Add test adding the output of two SFGs
Add text to the first doc page
Correct Delay documentation
Remove more C/C++-related stuff
Move GUI decorators to gui_utils
Add edit method to SFG and Schedule plus typing
Some typing fixes
Rename copy_component to copy
Rename replace_component to replace_operation
Remove C-based simulator for now
Add recent files for scheduler GUI
cbasedsim
cbasedsim
Remove UI-file for SFG GUI (and palette definitions)
Guirecentfiles
Minor cleanup
Add button to recompute the plot limits
resources.py: adjusted bar heights and exclusion graph drawing settings
fpl-2023
fpl-2023
resources.py: try-catch -> if cell not in cell_assignment
Fix linting issues
Add support for parallel interleaver generation
correct parameters 'rows' and 'columns' in generate_matrix_transposition()
Use enumerate
Fix documentation
Fix issue with schedule and Python >= 3.10
codegen: add functions 'write' and 'write_lines', reformat code
codegen: add pipelined back-edge mux decode logic to register based storage
codegen: add synchronous write address generation to memory based HDL generation
codegen: add B-ASIC commit hash in VHDL preamble
Start caching dependencies
aptcache
aptcache
Add VHDL testing
Replace truncate with quantize
codegen: add B-ASIC commit hash in VHDL preamble
codegen-commit-…
codegen-commit-hash
Fix minor documentation issues
codegen: VHDL generation for register based storage
codegen: VHDL generation for memory based storage
Add graph_color_cell_assignment method to ProcessCollection
Add left_edge_cell_assignment method to ProcessCollection
Remove unused arguments and parameters
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