process.py: add ABC MemoryProcess with support for spliting based on read times

This PR adds a new type of process ABC, MemoryProcess, to which the common code of MemoryVariable and PlainMemoryVariable is moved. MemoryProcess also lets the user split a process in two, based on the multiple read accesses that can exist in a MemoryProcess.

Related issues

• #251

Others

In the Comparison with folding memory assignment example, the add1.0 memory variable is now split into two memory variables, where the zero lifetime variable add1.0 is moved to direct_interconnect with split_on_length(length=0).

mem_vars = schedule.get_memory_variables()
direct, mem_vars = mem_vars.split_on_length()
for i, mem in enumerate(mem_vars_set):
    memory = Memory(mem, memory_type="RAM", entity_name=f"memory{i}")
    memory.assign("left_edge")
    memory.show_content(title=f"Assigned {memory.entity_name}")
direct.show(title="Direct interconnects")

Before:

After:

b_asic/codegen/vhdl/entity.py

@@ -55,7 +55,7 @@ def memory_based_storage(
     # Write the input port specification
     f.write(f'{2*VHDL_TAB}-- Memory port I/O\n')
     read_ports: set[Port] = set(
-        sum((mv.read_ports for mv in collection), ())
+        read_port for mv in collection for read_port in mv.read_ports
     )  # type: ignore
     for idx, read_port in enumerate(read_ports):
         port_name = read_port if isinstance(read_port, int) else read_port.name