WIP: VHDL code generation for register and memory based storages

b_asic/codegen/vhdl/architecture.py

@@ -4,7 +4,6 @@ Module for code generation of VHDL architectures.
 from io import TextIOWrapper
 from typing import Dict, Optional, Set, cast
 
-# from b_asic.codegen.vhdl_src import common
 from b_asic.codegen import vhdl
 from b_asic.codegen.vhdl import VHDL_TAB
 from b_asic.process import MemoryVariable, PlainMemoryVariable
@@ -199,13 +198,6 @@ def write_memory_based_storage(
         indent=len(VHDL_TAB),
         name='output_reg_proc',
     )
-    # if p_zero_exec:
-    #    f.write(f'{1*VHDL_TAB}p_0_out <=\n')
-    #    for p in filter(lambda p: p.execution_time==0, (p for pc in assignment for p in pc)):
-    #        f.write(f'{2*VHDL_TAB}p_0_in when schedule_cnt = {(p.start_time+1)%schedule_time} else\n')
-    #    f.write(f'{2*VHDL_TAB}read_port_0;\n')
-    # else:
-    #    f.write(f'{1*VHDL_TAB}p_0_out <= read_port_0;\n')
 
     f.write('\n')
     f.write(f'end architecture {architecture_name};')
@@ -300,10 +292,6 @@ def write_register_based_storage(
     f.write(f'{4*VHDL_TAB}when others => null;\n')
     f.write(f'{3*VHDL_TAB}end case;\n')
 
-    # for i in range(5):
-    #     forward_backward_table[
-    #     f.write(f'{3*VHDL_TAB}abc\n')
-
     vhdl.common.write_synchronous_process_epilogue(
         f,
         clk='clk',
@@ -335,10 +323,6 @@ def write_register_based_storage(
     f.write(f'{4*VHDL_TAB}when others => null;\n')
     f.write(f'{3*VHDL_TAB}end case;\n')
 
-    # for i in range(5):
-    #     forward_backward_table[
-    #     f.write(f'{3*VHDL_TAB}abc\n')
-
     vhdl.common.write_synchronous_process_epilogue(
         f,
         clk='clk',