test/test_outputport.py

@@ -6,75 +6,79 @@ import pytest
 
 @pytest.fixture
 def output_port():
-    return OutputPort(0, None)
+    return OutputPort(None, 0)
 
 @pytest.fixture
 def input_port():
-    return InputPort(0, None)
+    return InputPort(None, 0)
 
 @pytest.fixture
 def list_of_input_ports():
-    return [InputPort(_, None) for _ in range(0,3)]
+    return [InputPort(None, i) for i in range(0, 3)]
 
 class TestConnect:
     def test_multiple_ports(self, output_port, list_of_input_ports):
         """Can multiple ports connect to an output port?"""
         for port in list_of_input_ports:
-            output_port.connect(port)
+            port.connect(output_port)
 
-        assert output_port.signal_count() == len(list_of_input_ports)
+        assert output_port.signal_count == len(list_of_input_ports)
 
     def test_same_port(self, output_port, list_of_input_ports):
         """Check error handing."""
-        output_port.connect(list_of_input_ports[0])
-        with pytest.raises(AssertionError):
-            output_port.connect(list_of_input_ports[0])
+        list_of_input_ports[0].connect(output_port)
+        with pytest.raises(Exception):
+            list_of_input_ports[0].connect(output_port)
 
-        assert output_port.signal_count() == 2
+        assert output_port.signal_count == 1
 
 class TestAddSignal:
     def test_dangling(self, output_port):
         s = Signal()
         output_port.add_signal(s)
 
-        assert output_port.signal_count() == 1
-
-    def test_with_destination(self, output_port, input_port):
-        s = Signal(destination=input_port)
-        output_port.add_signal(s)
-
-        assert output_port.connected_ports == [s.destination]
+        assert output_port.signal_count == 1
+        assert output_port.signals == [s]
 
 class TestDisconnect:
-    def test_multiple_ports(self, output_port, list_of_input_ports):
+    def test_others_clear(self, output_port, list_of_input_ports):
         """Can multiple ports disconnect from OutputPort?"""
         for port in list_of_input_ports:
-            output_port.connect(port)
+            port.connect(output_port)
 
         for port in list_of_input_ports:
-            output_port.disconnect(port)
+            port.clear()
+
+        assert output_port.signal_count == 3
+        assert all(s.dangling() for s in output_port.signals)
 
-        assert output_port.signal_count() == 3
-        assert output_port.connected_ports == []
+    def test_self_clear(self, output_port, list_of_input_ports):
+        """Can an OutputPort disconnect from multiple ports?"""
+        for port in list_of_input_ports:
+            port.connect(output_port)
+
+        output_port.clear()
+
+        assert output_port.signal_count == 0
+        assert output_port.signals == []
 
 class TestRemoveSignal:
     def test_one_signal(self, output_port, input_port):
-        s = output_port.connect(input_port)
+        s = input_port.connect(output_port)
         output_port.remove_signal(s)
 
-        assert output_port.signal_count() == 0
+        assert output_port.signal_count == 0
         assert output_port.signals == []
-        assert output_port.connected_ports == []
 
     def test_multiple_signals(self, output_port, list_of_input_ports):
         """Can multiple signals disconnect from OutputPort?"""
         sigs = []
 
         for port in list_of_input_ports:
-            sigs.append(output_port.connect(port))
+            sigs.append(port.connect(output_port))
 
-        for sig in sigs:
-            output_port.remove_signal(sig)
+        for s in sigs:
+            output_port.remove_signal(s)
 
-        assert output_port.signal_count() == 0
+        assert output_port.signal_count == 0
         assert output_port.signals == []

test/test_sfg.py

+from b_asic import SFG
+from b_asic.signal import Signal
+from b_asic.core_operations import Addition, Constant, Multiplication
+from b_asic.special_operations import Input, Output
+
+
+class TestConstructor:
+    def test_direct_input_to_output_sfg_construction(self):
+        inp = Input("INP1")
+        out = Output(None, "OUT1")
+        out.input(0).connect(inp, "S1")
+
+        sfg = SFG(inputs=[inp], outputs=[out])
+
+        assert len(list(sfg.components)) == 3
+        assert sfg.input_count == 1
+        assert sfg.output_count == 1
+
+    def test_same_signal_input_and_output_sfg_construction(self):
+        add1 = Addition(None, None, "ADD1")
+        add2 = Addition(None, None, "ADD2")
+
+        sig1 = add2.input(0).connect(add1, "S1")
+
+        sfg = SFG(input_signals=[sig1], output_signals=[sig1])
+
+        assert len(list(sfg.components)) == 3
+        assert sfg.input_count == 1
+        assert sfg.output_count == 1
+
+    def test_outputs_construction(self, operation_tree):
+        outp = Output(operation_tree)
+        sfg = SFG(outputs=[outp])
+
+        assert len(list(sfg.components)) == 7
+        assert sfg.input_count == 0
+        assert sfg.output_count == 1
+
+    def test_signals_construction(self, operation_tree):
+        outs = Signal(source=operation_tree.output(0))
+        sfg = SFG(output_signals=[outs])
+
+        assert len(list(sfg.components)) == 7
+        assert sfg.input_count == 0
+        assert sfg.output_count == 1
+
+
+class TestDeepCopy:
+    def test_deep_copy_no_duplicates(self):
+        inp1 = Input("INP1")
+        inp2 = Input("INP2")
+        inp3 = Input("INP3")
+        add1 = Addition(inp1, inp2, "ADD1")
+        mul1 = Multiplication(add1, inp3, "MUL1")
+        out1 = Output(mul1, "OUT1")
+
+        mac_sfg = SFG(inputs=[inp1, inp2],
+                      outputs=[out1], name="mac_sfg")
+
+        mac_sfg_deep_copy = mac_sfg.deep_copy()
+
+        for g_id, component in mac_sfg._components_by_id.items():
+            component_copy = mac_sfg_deep_copy.find_by_id(g_id)
+            assert component.name == component_copy.name
+
+    def test_deep_copy(self):
+        inp1 = Input("INP1")
+        inp2 = Input("INP2")
+        inp3 = Input("INP3")
+        add1 = Addition(None, None, "ADD1")
+        add2 = Addition(None, None, "ADD2")
+        mul1 = Multiplication(None, None, "MUL1")
+        out1 = Output(None, "OUT1")
+
+        add1.input(0).connect(inp1, "S1")
+        add1.input(1).connect(inp2, "S2")
+        add2.input(0).connect(add1, "S4")
+        add2.input(1).connect(inp3, "S3")
+        mul1.input(0).connect(add1, "S5")
+        mul1.input(1).connect(add2, "S6")
+        out1.input(0).connect(mul1, "S7")
+
+        mac_sfg = SFG(inputs=[inp1, inp2],
+                      outputs=[out1], name="mac_sfg")
+
+        mac_sfg_deep_copy = mac_sfg.deep_copy()
+
+        for g_id, component in mac_sfg._components_by_id.items():
+            component_copy = mac_sfg_deep_copy.find_by_id(g_id)
+            assert component.name == component_copy.name
+
+    def test_deep_copy_no_duplicate_with_call(self):
+        inp1 = Input("INP1")
+        inp2 = Input("INP2")
+        inp3 = Input("INP3")
+        add1 = Addition(inp1, inp2, "ADD1")
+        mul1 = Multiplication(add1, inp3, "MUL1")
+        out1 = Output(mul1, "OUT1")
+
+        mac_sfg = SFG(inputs=[inp1, inp2],
+                      outputs=[out1], name="mac_sfg")
+
+        mac_sfg_deep_copy = mac_sfg()
+
+        for g_id, component in mac_sfg._components_by_id.items():
+            component_copy = mac_sfg_deep_copy.find_by_id(g_id)
+            assert component.name == component_copy.name
+
+    def test_deep_copy_with_call(self):
+        inp1 = Input("INP1")
+        inp2 = Input("INP2")
+        inp3 = Input("INP3")
+        add1 = Addition(None, None, "ADD1")
+        add2 = Addition(None, None, "ADD2")
+        mul1 = Multiplication(None, None, "MUL1")
+        out1 = Output(None, "OUT1")
+
+        add1.input(0).connect(inp1, "S1")
+        add1.input(1).connect(inp2, "S2")
+        add2.input(0).connect(add1, "S4")
+        add2.input(1).connect(inp3, "S3")
+        mul1.input(0).connect(add1, "S5")
+        mul1.input(1).connect(add2, "S6")
+        out1.input(0).connect(mul1, "S7")
+
+        mac_sfg = SFG(inputs=[inp1, inp2],
+                      outputs=[out1], name="mac_sfg")
+
+        mac_sfg_deep_copy = mac_sfg()
+
+        for g_id, component in mac_sfg._components_by_id.items():
+            component_copy = mac_sfg_deep_copy.find_by_id(g_id)
+            assert component.name == component_copy.name
+
+
+class TestComponents:
+
+    def test_advanced_components(self):
+        inp1 = Input("INP1")
+        inp2 = Input("INP2")
+        inp3 = Input("INP3")
+        add1 = Addition(None, None, "ADD1")
+        add2 = Addition(None, None, "ADD2")
+        mul1 = Multiplication(None, None, "MUL1")
+        out1 = Output(None, "OUT1")
+
+        add1.input(0).connect(inp1, "S1")
+        add1.input(1).connect(inp2, "S2")
+        add2.input(0).connect(add1, "S4")
+        add2.input(1).connect(inp3, "S3")
+        mul1.input(0).connect(add1, "S5")
+        mul1.input(1).connect(add2, "S6")
+        out1.input(0).connect(mul1, "S7")
+
+        mac_sfg = SFG(inputs=[inp1, inp2],
+                      outputs=[out1], name="mac_sfg")
+
+        assert set([comp.name for comp in mac_sfg.components]) == {
+            "INP1", "INP2", "INP3", "ADD1", "ADD2", "MUL1", "OUT1", "S1", "S2", "S3", "S4", "S5", "S6", "S7"}

test/test_signal.py

@@ -8,8 +8,8 @@ from b_asic.signal import Signal
 import pytest
 
 def test_signal_creation_and_disconnction_and_connection_changing():
-    in_port = InputPort(0, None)
-    out_port = OutputPort(1, None)
+    in_port = InputPort(None, 0)
+    out_port = OutputPort(None, 1)
     s = Signal(out_port, in_port)
 
     assert in_port.signals == [s]
@@ -17,7 +17,7 @@ def test_signal_creation_and_disconnction_and_connection_changing():
     assert s.source is out_port
     assert s.destination is in_port
 
-    in_port1 = InputPort(0, None)
+    in_port1 = InputPort(None, 0)
     s.set_destination(in_port1)
 
     assert in_port.signals == []
@@ -40,7 +40,7 @@ def test_signal_creation_and_disconnction_and_connection_changing():
     assert s.source is None
     assert s.destination is None
 
-    out_port1 = OutputPort(0, None)
+    out_port1 = OutputPort(None, 0)
     s.set_source(out_port1)
 
     assert out_port1.signals == [s]