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b991d33e

Commit b991d33e authored 2 years ago by Mikael Henriksson

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codegen: add synchronous write address generation to memory based HDL generation

parent f6ad95ac

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1 merge request!250Changes to code generation as a result of FPL-2023

Changes 4

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b_asic/codegen/vhdl/architecture.py 121 additions, 68 deletions

b_asic/codegen/vhdl/architecture.py
b_asic/codegen/vhdl/common.py 108 additions, 45 deletions

b_asic/codegen/vhdl/common.py
b_asic/resources.py 6 additions, 0 deletions

b_asic/resources.py
test/test_resources.py 1 addition, 1 deletion

test/test_resources.py

with 236 additions and 114 deletions

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