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Commit b0dbf845 authored by angloth's avatar angloth
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Add components test to sfg tests

parent 9eecfcc0
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5 merge requests!31Resolve "Specify internal input/output dependencies of an Operation",!25Resolve "System tests iteration 1",!24Resolve "System tests iteration 1",!23Resolve "Simulate SFG",!21Resolve "Print SFG"
Pipeline #12259 failed
......@@ -20,7 +20,7 @@ class TestConstructor:
add1 = Addition(None, None, "ADD1")
add2 = Addition(None, None, "ADD2")
sig1 = add2.input(0).connect(add1)
sig1 = add2.input(0).connect(add1, "S1")
sfg = SFG(input_signals=[sig1], output_signals=[sig1])
......@@ -88,3 +88,29 @@ class TestDeepCopy:
for g_id, component in mac_sfg._components_by_id.items():
component_copy = mac_sfg_deep_copy.find_by_id(g_id)
assert component.name == component_copy.name
class TestComponents:
def test_advanced_components(self):
inp1 = Input("INP1")
inp2 = Input("INP2")
inp3 = Input("INP3")
add1 = Addition(None, None, "ADD1")
add2 = Addition(None, None, "ADD2")
mul1 = Multiplication(None, None, "MUL1")
out1 = Output(None, "OUT1")
add1.input(0).connect(inp1, "S1")
add1.input(1).connect(inp2, "S2")
add2.input(0).connect(add1, "S4")
add2.input(1).connect(inp3, "S3")
mul1.input(0).connect(add1, "S5")
mul1.input(1).connect(add2, "S6")
out1.input(0).connect(mul1, "S7")
mac_sfg = SFG(inputs=[inp1, inp2],
outputs=[out1], name="mac_sfg")
assert set([comp.name for comp in mac_sfg.components]) == {
"INP1", "INP2", "INP3", "ADD1", "ADD2", "MUL1", "OUT1", "S1", "S2", "S3", "S4", "S5", "S6", "S7"}
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