codegen: add timeout test to matrix transposition tester

b_asic/codegen/testbench/streaming_matrix_transposition_tb.vhdl

@@ -47,6 +47,13 @@ begin
         wait;
     end process;
 
+    -- Timeout test
+    timeout_test_proc: process begin
+        wait until en = '1';
+        wait for 1 ms;
+        report "Timeout failure: 1 ms passed after enable=1" severity failure;
+    end process;
+
     -- Output testing
     output_test_proc: process begin
         wait until en = '1';

b_asic/codegen/vhdl/entity.py

@@ -43,7 +43,7 @@ def memory_based_storage(
     write_lines(
         f,
         [
-            (0, '-- Clock, synchronous reset and enable signals'),
+            (2, '-- Clock, synchronous reset and enable signals'),
             (2, 'clk : in std_logic;'),
             (2, 'rst : in std_logic;'),
             (2, 'en  : in std_logic;'),
@@ -53,9 +53,9 @@ def memory_based_storage(
 
     # Write the input port specification
     f.write(f'{2*VHDL_TAB}-- Memory port I/O\n')
-    read_ports: set[Port] = set(
+    read_ports: set[Port] = {
         read_port for mv in collection for read_port in mv.read_ports
-    )  # type: ignore
+    }  # type: ignore
     for idx, read_port in enumerate(read_ports):
         port_name = read_port if isinstance(read_port, int) else read_port.name
         port_name = 'p_' + str(port_name) + '_in'

b_asic/resources.py

@@ -1347,13 +1347,13 @@ class ProcessCollection:
         )
         adr_pipe_depth <= adr_pipe_depth if adr_pipe_depth else None
         if adr_mux_size is not None and adr_pipe_depth is not None:
-            if adr_mux_size <= 1:
+            if adr_mux_size <= 0:
                 raise ValueError(
-                    f'adr_mux_size={adr_mux_size} need to be greater than one'
+                    f'adr_mux_size={adr_mux_size} need to be greater than zero'
                 )
-            if adr_pipe_depth <= 0:
+            if adr_pipe_depth < 0:
                 raise ValueError(
-                    f'adr_pipe_depth={adr_pipe_depth} needs to be greater than zero'
+                    f'adr_pipe_depth={adr_pipe_depth} needs to be greater positive'
                 )
             if not input_sync:
                 raise ValueError('input_sync needs to be set to use address pipelining')

test/test_resources.py

@@ -83,16 +83,18 @@ class TestProcessCollectionPlainMemoryVariable:
         assert len(assignment_graph_color) == 16
 
     def test_generate_memory_based_vhdl(self):
+        # fmt: off
         variants = [
-            #  rows ,  cols , #mux , #pipe
-            # ----------------------------
-            (2, 2, None, None),
-            (3, 3, 2, 1),
-            (4, 4, 4, 1),
-            (5, 5, 4, 2),
-            (7, 7, 4, 3),
-            (4, 8, 2, 2),
+            #  rows ,  cols , #mux  , #pipe  #
+            # ------------------------------ #
+            (   2   ,   2   ,  None ,  None ),
+            (   3   ,   3   ,   1   ,   0   ),
+            (   4   ,   4   ,   4   ,   1   ),
+            (   5   ,   5   ,   4   ,   2   ),
+            (   7   ,   7   ,   4   ,   3   ),
+            (   4   ,   8   ,   2   ,   2   ),
         ]
+        # fmt: on
         for rows, cols, mux_size, pipe_depth in variants:
             collection = generate_matrix_transposer(
                 rows=rows, cols=cols, min_lifetime=0