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Commit 86454f36 authored by Adam Jakobsson's avatar Adam Jakobsson
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started on memory elements

parent 8da430f5
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......@@ -27,6 +27,7 @@ class Schema:
self._laps = dict()
self._cyclic = cyclic
self._resolution = resolution
self._memory_elements = dict()
if scheduling_alg == "ASAP":
self._schedule_asap()
......@@ -47,6 +48,8 @@ class Schema:
else:
self._schedule_time = schedule_time
self.get_memory_elements()
def start_time_of_operation(self, op_id: GraphID):
"""Get the start time of the operation with the specified by the op_id."""
assert op_id in self._start_times, "No operation with the specified op_id in this schema."
......@@ -105,3 +108,26 @@ class Schema:
op_start_time = max(op_start_time, op_start_time_from_in)
self._start_times[op.graph_id] = op_start_time
def get_memory_elements(self):
pl = self._sfg.get_precedence_list()
for port_list in pl:
for port in port_list:
time_list = []
for key in self._start_times:
if port.operation.graph_id == key:
for i in range(len(port.operation.outputs)-1):
time_list.append(self.start_times.get(port.operation.graph_id)+op.outputs[i].latency_offset)
for j in range(len(port.operation.outputs[i].signals)-1):
print(self._start_times.get(port.operation.outputs[i].signals[j].destination.operation.op_id))
time_list.append(self._start_times.get(port.operation.outputs[i].signals[j].destination.operation.op_id))
self._memory_elements[port.operation.outputs[i].signals[j].type_name] = time_list
time_list.pop() # remove end time if an output port has several signals as it's source
def print_memory_elements(self):
for key in self._memory_elements:
for value in self._memory_elements[key]:
print(key, value)
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