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Computer Engineering
B-ASIC - Better ASIC Toolbox
Commits
595bd54f
Commit
595bd54f
authored
1 year ago
by
Mikael Henriksson
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resources.py: add test to __str__
parent
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!279
resources.py: add test to __str__
Pipeline
#94053
passed
1 year ago
Stage: test
Stage: deploy
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2 changed files
b_asic/resources.py
+5
-3
5 additions, 3 deletions
b_asic/resources.py
test/test_resources.py
+26
-1
26 additions, 1 deletion
test/test_resources.py
with
31 additions
and
4 deletions
b_asic/resources.py
+
5
−
3
View file @
595bd54f
...
...
@@ -324,6 +324,11 @@ class _ForwardBackwardTable:
return
len
(
self
.
table
)
def
__str__
(
self
):
# ANSI escape codes for coloring in the forward-backward table stirng
GREEN_BACKGROUND_ANSI
=
"
\u001b
[42m
"
BROWN_BACKGROUND_ANSI
=
"
\u001b
[43m
"
RESET_BACKGROUND_ANSI
=
"
\033
[0m
"
# Text width of input and output column
def
lst_w
(
proc_lst
):
return
reduce
(
lambda
n
,
p
:
n
+
len
(
str
(
p
))
+
1
,
proc_lst
,
0
)
...
...
@@ -362,9 +367,6 @@ class _ForwardBackwardTable:
res
+=
f
'
{
inputs_str
:
^
{
input_col_w
-
1
}}
|
'
# Register columns
GREEN_BACKGROUND_ANSI
=
"
\u001b
[42m
"
BROWN_BACKGROUND_ANSI
=
"
\u001b
[43m
"
RESET_BACKGROUND_ANSI
=
"
\033
[0m
"
for
reg_idx
,
reg
in
enumerate
(
entry
.
regs
):
if
reg
is
None
:
res
+=
"
"
*
reg_col_w
+
"
|
"
...
...
This diff is collapsed.
Click to expand it.
test/test_resources.py
+
26
−
1
View file @
595bd54f
import
pickle
import
re
import
matplotlib.pyplot
as
plt
import
pytest
from
b_asic.process
import
PlainMemoryVariable
from
b_asic.research.interleaver
import
(
generate_matrix_transposer
,
generate_random_interleaver
,
)
from
b_asic.resources
import
ProcessCollection
from
b_asic.resources
import
ProcessCollection
,
_ForwardBackwardTable
class
TestProcessCollectionPlainMemoryVariable
:
...
...
@@ -83,6 +85,29 @@ class TestProcessCollectionPlainMemoryVariable:
word_length
=
16
,
)
def
test_forward_backward_table_to_string
(
self
):
collection
=
ProcessCollection
(
collection
=
{
PlainMemoryVariable
(
0
,
0
,
{
0
:
5
},
name
=
"
PC0
"
),
PlainMemoryVariable
(
1
,
0
,
{
0
:
4
},
name
=
"
PC1
"
),
PlainMemoryVariable
(
2
,
0
,
{
0
:
3
},
name
=
"
PC2
"
),
PlainMemoryVariable
(
3
,
0
,
{
0
:
6
},
name
=
"
PC3
"
),
PlainMemoryVariable
(
4
,
0
,
{
0
:
6
},
name
=
"
PC4
"
),
PlainMemoryVariable
(
5
,
0
,
{
0
:
5
},
name
=
"
PC5
"
),
},
schedule_time
=
7
,
cyclic
=
True
,
)
t
=
_ForwardBackwardTable
(
collection
)
process_names
=
{
match
.
group
(
0
)
for
match
in
re
.
finditer
(
r
'
PC[0-9]+
'
,
str
(
t
))}
register_names
=
{
match
.
group
(
0
)
for
match
in
re
.
finditer
(
r
'
R[0-9]+
'
,
str
(
t
))}
assert
len
(
process_names
)
==
6
# 6 process in the collection
assert
len
(
register_names
)
==
5
# 5 register required
for
i
,
process
in
enumerate
(
sorted
(
process_names
)):
assert
process
==
f
'
PC
{
i
}
'
for
i
,
register
in
enumerate
(
sorted
(
register_names
)):
assert
register
==
f
'
R
{
i
}
'
# Issue: #175
def
test_interleaver_issue175
(
self
):
with
open
(
'
test/fixtures/interleaver-two-port-issue175.p
'
,
'
rb
'
)
as
f
:
...
...
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