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3292e158

Commit 3292e158 authored 2 years ago by Mikael Henriksson

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codegen: add pipelined back-edge mux decode logic to register based storage

parent b991d33e

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1 merge request!250Changes to code generation as a result of FPL-2023

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b_asic/codegen/vhdl/__init__.py 27 additions, 0 deletions

b_asic/codegen/vhdl/__init__.py
b_asic/codegen/vhdl/architecture.py 93 additions, 28 deletions

b_asic/codegen/vhdl/architecture.py
b_asic/codegen/vhdl/common.py 22 additions, 23 deletions

b_asic/codegen/vhdl/common.py
b_asic/resources.py 4 additions, 1 deletion

b_asic/resources.py

with 146 additions and 52 deletions

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