Add architecture stub classes

b_asic/architecture.py

@@ -40,20 +40,15 @@ class ProcessingElement:
         self._operation_type = op_type
         self._type_name = op_type.type_name()
 
-    def write_code(self, path: str, entity_name: str):
+    def write_code(self, path: str, entity_name: str) -> None:
         """
-        Write VHDL code for memory.
+        Write VHDL code for processing element.
 
         Parameters
         ----------
         path : str
             Directory to write code in.
         entity_name : str
-
-        Returns
-        -------
-
-
         """
         raise NotImplementedError
 
@@ -84,7 +79,7 @@ class Memory:
         self._collection = process_collection
         self._memory_type = memory_type
 
-    def write_code(self, path: str, entity_name: str):
+    def write_code(self, path: str, entity_name: str) -> None:
         """
         Write VHDL code for memory.
 
@@ -127,7 +122,7 @@ class Architecture:
         self._memories = memories
         self._name = name
 
-    def write_code(self, path: str):
+    def write_code(self, path: str) -> None:
         """
         Write HDL of architecture.