Add architecture stub classes

b_asic/architecture.py

 """
 B-ASIC architecture classes.
 """
-from typing import Set
+from typing import Set, cast
 
 from b_asic.process import MemoryVariable, OperatorProcess, PlainMemoryVariable
 from b_asic.resources import ProcessCollection
@@ -25,18 +25,38 @@ class ProcessingElement:
             isinstance(operator, OperatorProcess)
             for operator in process_collection.collection
         ):
-            raise ValueError(
+            raise TypeError(
                 "Can only have OperatorProcesses in ProcessCollection when creating"
                 " ProcessingElement"
             )
-        ops = [operand.operation for operand in process_collection.collection]
+        ops = [
+            cast(operand, OperatorProcess).operation
+            for operand in process_collection.collection
+        ]
         op_type = type(ops[0])
         if not all(isinstance(op, op_type) for op in ops):
-            raise ValueError("Different Operation types in ProcessCollection")
+            raise TypeError("Different Operation types in ProcessCollection")
         self._collection = process_collection
         self._operation_type = op_type
         self._type_name = op_type.type_name()
 
+    def write_code(self, path: str, entity_name: str):
+        """
+        Write VHDL code for memory.
+
+        Parameters
+        ----------
+        path : str
+            Directory to write code in.
+        entity_name : str
+
+        Returns
+        -------
+
+
+        """
+        raise NotImplementedError
+
 
 class Memory:
     """
@@ -57,13 +77,30 @@ class Memory:
             isinstance(operator, (MemoryVariable, PlainMemoryVariable))
             for operator in process_collection.collection
         ):
-            raise ValueError(
+            raise TypeError(
                 "Can only have MemoryVariable or PlainMemoryVariable in"
                 " ProcessCollection when creating Memory"
             )
         self._collection = process_collection
         self._memory_type = memory_type
 
+    def write_code(self, path: str, entity_name: str):
+        """
+        Write VHDL code for memory.
+
+        Parameters
+        ----------
+        path : str
+            Directory to write code in.
+        entity_name : str
+
+        Returns
+        -------
+
+
+        """
+        raise NotImplementedError
+
 
 class Architecture:
     """
@@ -89,3 +126,14 @@ class Architecture:
         self._processing_elements = processing_elements
         self._memories = memories
         self._name = name
+
+    def write_code(self, path: str):
+        """
+        Write HDL of architecture.
+
+        Parameters
+        ----------
+        path : str
+            Directory to write code in.
+        """
+        raise NotImplementedError