diff --git a/place-and-route.tcl b/place-and-route.tcl
index 4330428d529ecf5fa2dd794d5366867de09cfadf..e51afd53ad5b9ccc310bbe4231268784f9745ecd 100644
--- a/place-and-route.tcl
+++ b/place-and-route.tcl
@@ -3,15 +3,16 @@
 # Author: Mikael Henriksson and Olle Hansson (2022)
 #
 
-set DESIGN_NAME "cd_top"
+set DESIGN_NAME "cd_top_reg"
 set MW_LIBRARY_NAME "${DESIGN_NAME}-lib"
 set VERILOG_NETLIST [list "${DESIGN_NAME}-post-synth.v"]
 set SDC_CONSTRAINT [list "${DESIGN_NAME}-post-synth.sdc"] 
 
 #
-# Maximum number of allowed cores during place-and-route
+# Maximum number of allowed cores during place-and-route. Linköping University (ISY) has a license limit of 16 cores
+# per place-and-route operation (as of Nov. 2022).
 #
-set_host_options -max_cores 20
+set_host_options -max_cores 16
 
 #
 # From the user manual 'Foundation_Synopsys_BE_TechnoKit_cmos028FDSOI_6U1x_2U2x_2T8x_LB_um.pdf':
@@ -47,7 +48,7 @@ read_sdc "$SDC_CONSTRAINT"
 # icc_shell> man create_floorplan
 # icc_shell> man create_rectilinear_rings
 #
-create_floorplan -control_type aspect_ratio -core_utilization 0.8
+create_floorplan -control_type aspect_ratio -core_utilization 0.5
 
 #
 # Place the cells within the floorplan. If placement fails
@@ -60,6 +61,7 @@ place_opt -effort high
 # Route all wires between the .
 # icc_shell> man route_opt
 #
+set_separate_process_option -routing false
 route_opt -effort high
 
 #