From f6ad95ac8a4021117294c8167a1c2b0412737230 Mon Sep 17 00:00:00 2001
From: Mikael Henriksson <mike.zx@hotmail.com>
Date: Wed, 15 Mar 2023 14:49:36 +0100
Subject: [PATCH] codegen: add B-ASIC commit hash in VHDL preamble
---
b_asic/codegen/vhdl/common.py | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/b_asic/codegen/vhdl/common.py b/b_asic/codegen/vhdl/common.py
index f6de8d8f..632fd959 100644
--- a/b_asic/codegen/vhdl/common.py
+++ b/b_asic/codegen/vhdl/common.py
@@ -4,6 +4,7 @@ Generation of common VHDL constructs
from datetime import datetime
from io import TextIOWrapper
+from subprocess import PIPE, Popen
from typing import Any, Optional, Set, Tuple
from b_asic.codegen.vhdl import VHDL_TAB
@@ -18,9 +19,18 @@ def write_b_asic_vhdl_preamble(f: TextIOWrapper):
f : :class:`io.TextIOWrapper`
The file object to write the header to.
"""
+ # Try to acquire the current git commit hash
+ git_commit_id = None
+ try:
+ process = Popen(['git', 'rev-parse', '--short', 'HEAD'], stdout=PIPE)
+ git_commit_id = process.communicate()[0].decode('utf-8').strip()
+ except:
+ pass
f.write(f'--\n')
f.write(f'-- This code was automatically generated by the B-ASIC toolbox.\n')
f.write(f'-- Code generation timestamp: ({datetime.now()})\n')
+ if git_commit_id:
+ f.write(f'-- B-ASIC short commit hash: {git_commit_id}\n')
f.write(f'-- URL: https://gitlab.liu.se/da/B-ASIC\n')
f.write(f'--\n\n')
--
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