From cf40c5d7aa79446a7a1735ea653720ab77e719fd Mon Sep 17 00:00:00 2001
From: Mikael Henriksson <mike.zx@hotmail.com>
Date: Fri, 18 Aug 2023 09:04:17 +0200
Subject: [PATCH] codegen: increase length of matrix transposition unit test
---
.../streaming_matrix_transposition_tb.vhdl | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/b_asic/codegen/testbench/streaming_matrix_transposition_tb.vhdl b/b_asic/codegen/testbench/streaming_matrix_transposition_tb.vhdl
index 398a5007..e91a898d 100644
--- a/b_asic/codegen/testbench/streaming_matrix_transposition_tb.vhdl
+++ b/b_asic/codegen/testbench/streaming_matrix_transposition_tb.vhdl
@@ -40,7 +40,7 @@ begin
-- Input generation
input_gen_proc: process begin
wait until en = '1';
- for i in 0 to ROWS*COLS-1 loop
+ for i in 0 to 4*ROWS*COLS-1 loop
wait until clk = '0';
input <= std_logic_vector(to_unsigned(i, input'length));
end loop;
@@ -51,10 +51,17 @@ begin
output_test_proc: process begin
wait until en = '1';
wait until output = std_logic_vector(to_unsigned(0, output'length));
- for col in 0 to COLS-1 loop
- for row in 0 to ROWS-1 loop
- wait until clk = '0';
- --check(output = std_logic_vector(to_unsigned(row*COLS + col, output'length)));
+ for i in 0 to 3 loop
+ for col in 0 to COLS-1 loop
+ for row in 0 to ROWS-1 loop
+ wait until clk = '0';
+ check(
+ output =
+ std_logic_vector(
+ to_unsigned(i*ROWS*COLS + row*COLS + col, output'length)
+ )
+ );
+ end loop;
end loop;
end loop;
done <= true;
--
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