diff --git a/b_asic/signal_flow_graph.py b/b_asic/signal_flow_graph.py
index a9599e10bd669067ef14e542a1097b38f4485fad..b4c556079feec8bfd68e135621d9e85b623fb427 100644
--- a/b_asic/signal_flow_graph.py
+++ b/b_asic/signal_flow_graph.py
@@ -64,8 +64,8 @@ class GraphIDGenerator:
def next_id(self, type_name: TypeName, used_ids: MutableSet = set()) -> GraphID:
"""Get the next graph id for a certain graph id type."""
- self._next_id_number[type_name] += 1
new_id = type_name + str(self._next_id_number[type_name])
+ self._next_id_number[type_name] += 1
while new_id in used_ids:
self._next_id_number[type_name] += 1
new_id = type_name + str(self._next_id_number[type_name])
diff --git a/examples/firstorderiirfilter.py b/examples/firstorderiirfilter.py
index 4dea6dcf8bf1e53e0ce6a7b33ae062165a0fb3e2..3a2ed744a1a05b149a7de0c97444d2a633126ff9 100644
--- a/examples/firstorderiirfilter.py
+++ b/examples/firstorderiirfilter.py
@@ -78,59 +78,59 @@ firstorderiir.print_precedence_graph()
#
# .. graphviz::
#
-# digraph {
-# rankdir=LR
-# subgraph cluster_0 {
-# label=N0
-# "in1.0" [label=in1 height=0.1 shape=rectangle width=0.1]
-# "t1.0" [label=t1 height=0.1 shape=rectangle width=0.1]
-# }
-# subgraph cluster_1 {
-# label=N1
-# "cmul2.0" [label=cmul2 height=0.1 shape=rectangle width=0.1]
-# "cmul1.0" [label=cmul1 height=0.1 shape=rectangle width=0.1]
-# }
-# subgraph cluster_2 {
-# label=N2
-# "add1.0" [label=add1 height=0.1 shape=rectangle width=0.1]
-# }
-# subgraph cluster_3 {
-# label=N3
-# "add2.0" [label=add2 height=0.1 shape=rectangle width=0.1]
-# }
-# "in1.0" -> add1
-# add1 [label=add1 shape=ellipse]
-# in1 -> "in1.0"
-# in1 [label=in1 shape=cds]
-# "t1.0" -> cmul2
-# cmul2 [label=cmul2 shape=ellipse]
-# "t1.0" -> cmul1
-# cmul1 [label=cmul1 shape=ellipse]
-# t1Out -> "t1.0"
-# t1Out [label=t1 shape=square]
-# "cmul2.0" -> add2
-# add2 [label=add2 shape=ellipse]
-# cmul2 -> "cmul2.0"
-# cmul2 [label=cmul2 shape=ellipse]
-# "cmul1.0" -> add1
-# add1 [label=add1 shape=ellipse]
-# cmul1 -> "cmul1.0"
-# cmul1 [label=cmul1 shape=ellipse]
-# "add1.0" -> t1In
-# t1In [label=t1 shape=square]
-# "add1.0" -> add2
-# add2 [label=add2 shape=ellipse]
-# add1 -> "add1.0"
-# add1 [label=add1 shape=ellipse]
-# "add2.0" -> out1
-# out1 [label=out1 shape=cds]
-# add2 -> "add2.0"
-# add2 [label=add2 shape=ellipse]
-# }
-#
+# digraph {
+# rankdir=LR
+# subgraph cluster_0 {
+# label=N0
+# "in0.0" [label=in0 height=0.1 shape=rectangle width=0.1]
+# "t0.0" [label=t0 height=0.1 shape=rectangle width=0.1]
+# }
+# subgraph cluster_1 {
+# label=N1
+# "cmul1.0" [label=cmul1 height=0.1 shape=rectangle width=0.1]
+# "cmul0.0" [label=cmul0 height=0.1 shape=rectangle width=0.1]
+# }
+# subgraph cluster_2 {
+# label=N2
+# "add0.0" [label=add0 height=0.1 shape=rectangle width=0.1]
+# }
+# subgraph cluster_3 {
+# label=N3
+# "add1.0" [label=add1 height=0.1 shape=rectangle width=0.1]
+# }
+# "in0.0" -> add0
+# add0 [label=add0 shape=ellipse]
+# in0 -> "in0.0"
+# in0 [label=in0 shape=cds]
+# "t0.0" -> cmul1
+# cmul1 [label=cmul1 shape=ellipse]
+# "t0.0" -> cmul0
+# cmul0 [label=cmul0 shape=ellipse]
+# t0Out -> "t0.0"
+# t0Out [label=t0 shape=square]
+# "cmul1.0" -> add1
+# add1 [label=add1 shape=ellipse]
+# cmul1 -> "cmul1.0"
+# cmul1 [label=cmul1 shape=ellipse]
+# "cmul0.0" -> add0
+# add0 [label=add0 shape=ellipse]
+# cmul0 -> "cmul0.0"
+# cmul0 [label=cmul0 shape=ellipse]
+# "add0.0" -> t0In
+# t0In [label=t0 shape=square]
+# "add0.0" -> add1
+# add1 [label=add1 shape=ellipse]
+# add0 -> "add0.0"
+# add0 [label=add0 shape=ellipse]
+# "add1.0" -> out0
+# out0 [label=out0 shape=cds]
+# add1 -> "add1.0"
+# add1 [label=add1 shape=ellipse]
+# }
+#
# As seen, each operation has an id, in addition to the optional name.
# This can be used to access the operation. For example,
-firstorderiir.find_by_id('cmul1')
+firstorderiir.find_by_id('cmul0')
# %%
# Note that this operation differs from ``a1`` defined above as the operations are
@@ -170,7 +170,7 @@ sim.results
import matplotlib.pyplot as plt # noqa: E402
plt.plot(sim.results['0'], label="Output")
-plt.plot(sim.results['add1'], label="After first addition")
+plt.plot(sim.results['add0'], label="After first addition")
plt.legend()
plt.show()
diff --git a/examples/fivepointwinograddft.py b/examples/fivepointwinograddft.py
index dea0cd55b2bb917bbdee5c629f19cb8bae9433d9..0787445ebb37df54947e2f0eada6513d98dbdac7 100644
--- a/examples/fivepointwinograddft.py
+++ b/examples/fivepointwinograddft.py
@@ -80,54 +80,54 @@ schedule.show()
# Reschedule to only use one AddSub and one multiplier
schedule.set_schedule_time(10)
-schedule.move_operation('out5', 12)
-schedule.move_operation('out4', 11)
-schedule.move_operation('out3', 10)
-schedule.move_operation('out2', 9)
-schedule.move_operation('out1', 12)
-schedule.move_operation('bfly4', 10)
-schedule.move_operation('bfly3', 9)
-schedule.move_operation('bfly2', 7)
-schedule.move_operation('addsub5', 5)
-schedule.move_operation('addsub3', 5)
+schedule.move_operation('out4', 12)
+schedule.move_operation('out3', 11)
+schedule.move_operation('out2', 10)
+schedule.move_operation('out1', 9)
+schedule.move_operation('out0', 12)
+schedule.move_operation('bfly3', 10)
+schedule.move_operation('bfly2', 9)
+schedule.move_operation('bfly1', 7)
+schedule.move_operation('addsub4', 5)
schedule.move_operation('addsub2', 5)
-schedule.move_operation('cmul5', 4)
-schedule.move_operation('cmul3', 4)
-schedule.move_operation('cmul1', 5)
-schedule.move_operation('addsub1', 6)
-schedule.move_operation('cmul2', 6)
-schedule.move_operation('addsub4', 4)
-schedule.move_operation('bfly1', 4)
-schedule.move_operation('cmul4', 6)
-schedule.move_operation('bfly6', 4)
+schedule.move_operation('addsub1', 5)
+schedule.move_operation('cmul4', 4)
+schedule.move_operation('cmul2', 4)
+schedule.move_operation('cmul0', 5)
+schedule.move_operation('addsub0', 6)
+schedule.move_operation('cmul1', 6)
+schedule.move_operation('addsub3', 4)
+schedule.move_operation('bfly0', 4)
+schedule.move_operation('cmul3', 6)
schedule.move_operation('bfly5', 4)
-schedule.move_operation('in2', 1)
-schedule.move_operation('in3', 2)
-schedule.move_operation('in4', 3)
-schedule.move_operation('in5', 4)
-schedule.move_operation('bfly6', -1)
-schedule.move_operation('bfly4', 1)
-schedule.move_operation('cmul3', 1)
-schedule.move_operation('cmul5', 1)
-schedule.move_operation('bfly1', 1)
+schedule.move_operation('bfly4', 4)
+schedule.move_operation('in1', 1)
+schedule.move_operation('in2', 2)
+schedule.move_operation('in3', 3)
+schedule.move_operation('in4', 4)
+schedule.move_operation('bfly5', -1)
+schedule.move_operation('bfly3', 1)
+schedule.move_operation('cmul2', 1)
+schedule.move_operation('cmul4', 1)
+schedule.move_operation('bfly0', 1)
+schedule.move_operation('addsub0', -1)
+schedule.move_operation('cmul1', -3)
+schedule.move_operation('cmul3', -2)
+schedule.move_operation('cmul4', -1)
+schedule.move_operation('addsub4', 1)
+schedule.move_operation('addsub1', 2)
+schedule.move_operation('cmul0', 1)
+schedule.move_operation('bfly0', -1)
+schedule.move_operation('addsub0', -1)
+schedule.move_operation('bfly2', -1)
+schedule.move_operation('cmul2', -1)
+schedule.move_operation('cmul4', 1)
+schedule.move_operation('addsub2', -1)
+schedule.move_operation('addsub4', -1)
schedule.move_operation('addsub1', -1)
-schedule.move_operation('cmul2', -3)
-schedule.move_operation('cmul4', -2)
-schedule.move_operation('cmul5', -1)
-schedule.move_operation('addsub5', 1)
-schedule.move_operation('addsub2', 2)
-schedule.move_operation('cmul1', 1)
schedule.move_operation('bfly1', -1)
-schedule.move_operation('addsub1', -1)
+schedule.move_operation('bfly2', -2)
schedule.move_operation('bfly3', -1)
-schedule.move_operation('cmul3', -1)
-schedule.move_operation('cmul5', 1)
-schedule.move_operation('addsub3', -1)
-schedule.move_operation('addsub5', -1)
-schedule.move_operation('addsub2', -1)
-schedule.move_operation('bfly2', -1)
-schedule.move_operation('bfly3', -2)
-schedule.move_operation('bfly4', -1)
schedule.show()
# %%
diff --git a/examples/folding_example_with_architecture.py b/examples/folding_example_with_architecture.py
index 289b9d1cef4e75743eba5c9a41a6f64a03227bfe..9baf92e0162d91167012b10314815f5e9312125b 100644
--- a/examples/folding_example_with_architecture.py
+++ b/examples/folding_example_with_architecture.py
@@ -53,17 +53,17 @@ schedule.show(title='Original schedule')
# %%
# Reschedule to only require one adder and one multiplier
-schedule.move_operation('out1', 2)
-schedule.move_operation('add3', 2)
-schedule.move_operation('cmul3', -3)
-schedule.move_operation('add4', 3)
+schedule.move_operation('out0', 2)
+schedule.move_operation('add2', 2)
schedule.move_operation('cmul2', -3)
+schedule.move_operation('add3', 3)
+schedule.move_operation('cmul1', -3)
schedule.set_schedule_time(4)
-schedule.move_operation('cmul2', 1)
-schedule.move_operation('cmul1', 1)
-schedule.move_operation('in1', 3)
-schedule.move_operation('cmul3', -1)
schedule.move_operation('cmul1', 1)
+schedule.move_operation('cmul0', 1)
+schedule.move_operation('in0', 3)
+schedule.move_operation('cmul2', -1)
+schedule.move_operation('cmul0', 1)
schedule.show(title='Improved schedule')
# %%
diff --git a/examples/secondorderdirectformiir_architecture.py b/examples/secondorderdirectformiir_architecture.py
index 72d23961bcc44c681af4688f545b690900f47945..a60c760d0149de36a6b6008933c0baa098f1b275 100644
--- a/examples/secondorderdirectformiir_architecture.py
+++ b/examples/secondorderdirectformiir_architecture.py
@@ -47,11 +47,11 @@ schedule.show(title='Original schedule')
# %%
# Reschedule to only require one adder and one multiplier.
-schedule.move_operation('add4', 2)
-schedule.move_operation('cmul5', -4)
-schedule.move_operation('cmul4', -5)
-schedule.move_operation('cmul6', -2)
-schedule.move_operation('cmul3', 1)
+schedule.move_operation('add3', 2)
+schedule.move_operation('cmul4', -4)
+schedule.move_operation('cmul3', -5)
+schedule.move_operation('cmul5', -2)
+schedule.move_operation('cmul2', 1)
schedule.show(title='Improved schedule')
# %%
@@ -100,11 +100,11 @@ arch = Architecture(
arch
# %%
-# To reduce the amount of interconnect, the ``cuml3.0`` variable can be moved from
+# To reduce the amount of interconnect, the ``cuml2.0`` variable can be moved from
# ``memory0`` to ``memory2``. In this way, ``memory0`` only gets variables from the
# adder and an input multiplexer can be avoided. The memories must be assigned again as
# the contents have changed.
-arch.move_process('cmul3.0', 'memory0', 'memory2')
+arch.move_process('cmul2.0', 'memory0', 'memory2')
memories[0].assign()
memories[2].assign()
@@ -117,9 +117,9 @@ memories[2].show_content("New assigned memory2")
arch
# %%
-# It is of course also possible to move ``add4.0`` to ``memory2`` to save one memory
+# It is of course also possible to move ``add3.0`` to ``memory2`` to save one memory
# cell. It is possible to pass ``assign=True`` to perform assignment after moving.
-arch.move_process('add4.0', 'memory0', 'memory2', assign=True)
+arch.move_process('add3.0', 'memory0', 'memory2', assign=True)
memories[0].show_content("New assigned memory0")
memories[2].show_content("New assigned memory2")
@@ -129,9 +129,9 @@ memories[2].show_content("New assigned memory2")
arch
# %%
-# Finally, by noting that ``cmul1.0`` is the only variable from ``memory1`` going to
+# Finally, by noting that ``cmul0.0`` is the only variable from ``memory1`` going to
# ``in0`` of ``adder``, another multiplexer can be reduced by:
-arch.move_process('cmul1.0', 'memory1', 'memory2', assign=True)
+arch.move_process('cmul0.0', 'memory1', 'memory2', assign=True)
memories[1].show_content("New assigned memory1")
memories[2].show_content("New assigned memory2")
diff --git a/examples/threepointwinograddft.py b/examples/threepointwinograddft.py
index ff5cfa5a1bbc8fa4586a4a2f28921003912633f0..38338b0894bbe58f482668f6ca3a7a9d4c34fe14 100644
--- a/examples/threepointwinograddft.py
+++ b/examples/threepointwinograddft.py
@@ -59,40 +59,40 @@ schedule.show()
# Reschedule to only use one AddSub and one multiplier
schedule.set_schedule_time(10)
-schedule.move_operation('out2', 3)
-schedule.move_operation('out3', 4)
-schedule.move_operation('addsub5', 2)
-schedule.move_operation('addsub4', 3)
-schedule.move_operation('addsub3', 2)
-schedule.move_operation('cmul2', 2)
-schedule.move_operation('cmul1', 2)
-schedule.move_operation('out1', 5)
-schedule.move_operation('addsub1', 3)
-schedule.move_operation('addsub6', 2)
+schedule.move_operation('out1', 3)
+schedule.move_operation('out2', 4)
+schedule.move_operation('addsub4', 2)
+schedule.move_operation('addsub3', 3)
schedule.move_operation('addsub2', 2)
-schedule.move_operation('in2', 1)
-schedule.move_operation('in3', 2)
-schedule.move_operation('cmul2', 1)
-schedule.move_operation('out3', 6)
+schedule.move_operation('cmul1', 2)
+schedule.move_operation('cmul0', 2)
+schedule.move_operation('out0', 5)
+schedule.move_operation('addsub0', 3)
+schedule.move_operation('addsub5', 2)
+schedule.move_operation('addsub1', 2)
+schedule.move_operation('in1', 1)
+schedule.move_operation('in2', 2)
+schedule.move_operation('cmul1', 1)
schedule.move_operation('out2', 6)
schedule.move_operation('out1', 6)
-schedule.move_operation('addsub6', 1)
-schedule.move_operation('addsub4', 3)
-schedule.move_operation('addsub5', 4)
-schedule.move_operation('addsub4', 1)
-schedule.move_operation('addsub5', 4)
-schedule.move_operation('cmul2', 3)
-schedule.move_operation('addsub4', 2)
-schedule.move_operation('cmul2', 3)
-schedule.move_operation('addsub3', 5)
+schedule.move_operation('out0', 6)
+schedule.move_operation('addsub5', 1)
+schedule.move_operation('addsub3', 3)
+schedule.move_operation('addsub4', 4)
+schedule.move_operation('addsub3', 1)
+schedule.move_operation('addsub4', 4)
+schedule.move_operation('cmul1', 3)
+schedule.move_operation('addsub3', 2)
+schedule.move_operation('cmul1', 3)
+schedule.move_operation('addsub2', 5)
schedule.set_schedule_time(6)
-schedule.move_operation('addsub1', 1)
-schedule.move_operation('addsub4', -1)
-schedule.move_operation('cmul2', -2)
-schedule.move_operation('addsub4', -1)
-schedule.move_operation('addsub1', -1)
+schedule.move_operation('addsub0', 1)
+schedule.move_operation('addsub3', -1)
+schedule.move_operation('cmul1', -2)
schedule.move_operation('addsub3', -1)
-schedule.move_operation('addsub5', -4)
+schedule.move_operation('addsub0', -1)
+schedule.move_operation('addsub2', -1)
+schedule.move_operation('addsub4', -4)
schedule.show()
# Extract memory variables and operation executions
@@ -139,8 +139,8 @@ arch
# %%
# Move memory variables
-arch.move_process('addsub2.0', memories[2], memories[1])
-arch.move_process('addsub4.0', memories[1], memories[2], assign=True)
+arch.move_process('addsub1.0', memories[2], memories[1])
+arch.move_process('addsub3.0', memories[1], memories[2], assign=True)
memories[1].assign()
memories[1].show_content(title="Assigned memory1")
diff --git a/examples/twotapfirsfg.py b/examples/twotapfirsfg.py
index 87a90e1c340add655b42c14660bed860e85a4ed6..3d8b6b7eba6b879dab801cfd08f438b5ce410209 100644
--- a/examples/twotapfirsfg.py
+++ b/examples/twotapfirsfg.py
@@ -14,40 +14,40 @@ from b_asic import (
)
# Inputs:
-in1 = Input(name="in_1")
+in0 = Input(name="in_0")
# Outputs:
-out1 = Output(name="out1")
+out0 = Output(name="out0")
# Operations:
-t1 = Delay(initial_value=0, name="t1")
-cmul1 = ConstantMultiplication(
- value=0.5, name="cmul1", latency_offsets={'in0': None, 'out0': None}
+t0 = Delay(initial_value=0, name="t0")
+cmul0 = ConstantMultiplication(
+ value=0.5, name="cmul0", latency_offsets={'in0': None, 'out0': None}
)
-add1 = Addition(
- name="add1", latency_offsets={'in0': None, 'in1': None, 'out0': None}
+add0 = Addition(
+ name="add0", latency_offsets={'in0': None, 'in1': None, 'out0': None}
)
-cmul2 = ConstantMultiplication(
- value=0.5, name="cmul2", latency_offsets={'in0': None, 'out0': None}
+cmul1 = ConstantMultiplication(
+ value=0.5, name="cmul1", latency_offsets={'in0': None, 'out0': None}
)
# Signals:
-Signal(source=t1.output(0), destination=cmul1.input(0))
-Signal(source=in1.output(0), destination=t1.input(0))
-Signal(source=in1.output(0), destination=cmul2.input(0))
-Signal(source=cmul1.output(0), destination=add1.input(0))
-Signal(source=add1.output(0), destination=out1.input(0))
-Signal(source=cmul2.output(0), destination=add1.input(1))
-twotapfir = SFG(inputs=[in1], outputs=[out1], name='twotapfir')
+Signal(source=t0.output(0), destination=cmul0.input(0))
+Signal(source=in0.output(0), destination=t0.input(0))
+Signal(source=in0.output(0), destination=cmul1.input(0))
+Signal(source=cmul0.output(0), destination=add0.input(0))
+Signal(source=add0.output(0), destination=out0.input(0))
+Signal(source=cmul1.output(0), destination=add0.input(1))
+twotapfir = SFG(inputs=[in0], outputs=[out0], name='twotapfir')
# SFG Properties:
prop = {'name': twotapfir}
positions = {
- 't1': (-209, 19),
- 'cmul1': (-95, 76),
- 'add1': (0, 95),
- 'cmul2': (-209, 114),
- 'out1': (76, 95),
- 'in1': (-323, 19),
+ 't0': (-209, 19),
+ 'cmul0': (-95, 76),
+ 'add0': (0, 95),
+ 'cmul1': (-209, 114),
+ 'out0': (76, 95),
+ 'in0': (-323, 19),
}
diff --git a/test/baseline/test__get_figure_no_execution_times.png b/test/baseline/test__get_figure_no_execution_times.png
index 684557d2a3b49951e2e3f8cb919724308035f1f7..bfe81db6ffd39001bbe01f50e4a13530bf38d16c 100644
Binary files a/test/baseline/test__get_figure_no_execution_times.png and b/test/baseline/test__get_figure_no_execution_times.png differ
diff --git a/test/baseline/test_draw_matrix_transposer_4.png b/test/baseline/test_draw_matrix_transposer_4.png
index c8ee191a8593d0420a55a3883a76ed86290e2256..7c2c59a58eefde33df86de184688f3cdbe3a8b93 100644
Binary files a/test/baseline/test_draw_matrix_transposer_4.png and b/test/baseline/test_draw_matrix_transposer_4.png differ
diff --git a/test/baseline/test_draw_process_collection.png b/test/baseline/test_draw_process_collection.png
index 4b82425c023beadbf4b822c9c236852738ee2fce..538978b1a5702794e5fce020425b7b019c39ead3 100644
Binary files a/test/baseline/test_draw_process_collection.png and b/test/baseline/test_draw_process_collection.png differ
diff --git a/test/baseline/test_left_edge_cell_assignment.png b/test/baseline/test_left_edge_cell_assignment.png
index 45420a64ac885227c686564337c2be329830e71e..45e5846b3da869fecc614a3009a42273dd1a9ae4 100644
Binary files a/test/baseline/test_left_edge_cell_assignment.png and b/test/baseline/test_left_edge_cell_assignment.png differ
diff --git a/test/fixtures/schedule.py b/test/fixtures/schedule.py
index f6ec65bf677825bdb06b61aa426ba3f893c315a1..e11b95c9e2d8bdfcd57fdb7d93f6f82aed45b779 100644
--- a/test/fixtures/schedule.py
+++ b/test/fixtures/schedule.py
@@ -38,14 +38,14 @@ def schedule_direct_form_iir_lp_filter(sfg_direct_form_iir_lp_filter: SFG):
ConstantMultiplication.type_name(), 1
)
schedule = Schedule(sfg_direct_form_iir_lp_filter, algorithm="ASAP", cyclic=True)
- schedule.move_operation('cmul4', -1)
schedule.move_operation('cmul3', -1)
- schedule.move_operation('cmul4', -10)
- schedule.move_operation('cmul4', 1)
- schedule.move_operation('cmul3', -8)
- schedule.move_operation('add4', 1)
- schedule.move_operation('add4', 1)
- schedule.move_operation('cmul2', 1)
- schedule.move_operation('cmul2', 1)
- schedule.move_operation('cmul4', 2)
+ schedule.move_operation('cmul2', -1)
+ schedule.move_operation('cmul3', -10)
+ schedule.move_operation('cmul3', 1)
+ schedule.move_operation('cmul2', -8)
+ schedule.move_operation('add3', 1)
+ schedule.move_operation('add3', 1)
+ schedule.move_operation('cmul1', 1)
+ schedule.move_operation('cmul1', 1)
+ schedule.move_operation('cmul3', 2)
return schedule
diff --git a/test/test_architecture.py b/test/test_architecture.py
index 3b0d9180a878d651e91aeca048593a68ecfb371b..d2917d08bde5b0952a94a6c9108e097d2d0c9c03 100644
--- a/test/test_architecture.py
+++ b/test/test_architecture.py
@@ -212,29 +212,29 @@ def test_move_process(schedule_direct_form_iir_lp_filter: Schedule):
)
# Some movement that must work
- assert memories[1].collection.from_name('cmul4.0')
- architecture.move_process('cmul4.0', memories[1], memories[0])
- assert memories[0].collection.from_name('cmul4.0')
+ assert memories[1].collection.from_name('cmul3.0')
+ architecture.move_process('cmul3.0', memories[1], memories[0])
+ assert memories[0].collection.from_name('cmul3.0')
- assert memories[1].collection.from_name('in1.0')
- architecture.move_process('in1.0', memories[1], memories[0])
- assert memories[0].collection.from_name('in1.0')
+ assert memories[1].collection.from_name('in0.0')
+ architecture.move_process('in0.0', memories[1], memories[0])
+ assert memories[0].collection.from_name('in0.0')
- assert processing_elements[1].collection.from_name('add1')
- architecture.move_process('add1', processing_elements[1], processing_elements[0])
- assert processing_elements[0].collection.from_name('add1')
+ assert processing_elements[1].collection.from_name('add0')
+ architecture.move_process('add0', processing_elements[1], processing_elements[0])
+ assert processing_elements[0].collection.from_name('add0')
# Processes leave the resources they have moved from
with pytest.raises(KeyError):
- memories[1].collection.from_name('cmul4.0')
+ memories[1].collection.from_name('cmul3.0')
with pytest.raises(KeyError):
- memories[1].collection.from_name('in1.0')
+ memories[1].collection.from_name('in0.0')
with pytest.raises(KeyError):
- processing_elements[1].collection.from_name('add1')
+ processing_elements[1].collection.from_name('add0')
# Processes can only be moved when the source and destination process-types match
- with pytest.raises(TypeError, match="cmul4.0 not of type"):
- architecture.move_process('cmul4.0', memories[0], processing_elements[0])
+ with pytest.raises(TypeError, match="cmul3.0 not of type"):
+ architecture.move_process('cmul3.0', memories[0], processing_elements[0])
with pytest.raises(KeyError, match="invalid_name not in"):
architecture.move_process('invalid_name', memories[0], processing_elements[1])
diff --git a/test/test_graph_id_generator.py b/test/test_graph_id_generator.py
index 029fe6e7c93cd1baff630591959940e2bef384dd..5c57c10a40c9201236225f95ce607a46cb72bb58 100644
--- a/test/test_graph_id_generator.py
+++ b/test/test_graph_id_generator.py
@@ -15,17 +15,17 @@ def graph_id_generator():
class TestGetNextId:
def test_empty_string_generator(self, graph_id_generator):
"""Test the graph id generator for an empty string type."""
+ assert graph_id_generator.next_id("") == "0"
assert graph_id_generator.next_id("") == "1"
- assert graph_id_generator.next_id("") == "2"
def test_normal_string_generator(self, graph_id_generator):
""" "Test the graph id generator for a normal string type."""
+ assert graph_id_generator.next_id("add") == "add0"
assert graph_id_generator.next_id("add") == "add1"
- assert graph_id_generator.next_id("add") == "add2"
def test_different_strings_generator(self, graph_id_generator):
"""Test the graph id generator for different strings."""
+ assert graph_id_generator.next_id("sub") == "sub0"
+ assert graph_id_generator.next_id("mul") == "mul0"
assert graph_id_generator.next_id("sub") == "sub1"
assert graph_id_generator.next_id("mul") == "mul1"
- assert graph_id_generator.next_id("sub") == "sub2"
- assert graph_id_generator.next_id("mul") == "mul2"
diff --git a/test/test_process.py b/test/test_process.py
index 7ed1517957eda987811da881af8c84e2983dfc32..92a4eed176a4c5e523ee22a10d76228ea9e85eae 100644
--- a/test/test_process.py
+++ b/test/test_process.py
@@ -28,9 +28,9 @@ def test_MemoryVariables(secondorder_iir_schedule):
mem_vars = pc.collection
pattern = re.compile(
"MemoryVariable\\(3, <b_asic.port.OutputPort object at 0x[a-fA-F0-9]+>,"
- " {<b_asic.port.InputPort object at 0x[a-fA-F0-9]+>: 4}, 'cmul1.0'\\)"
+ " {<b_asic.port.InputPort object at 0x[a-fA-F0-9]+>: 4}, 'cmul0.0'\\)"
)
- mem_var = [m for m in mem_vars if m.name == 'cmul1.0'][0]
+ mem_var = [m for m in mem_vars if m.name == 'cmul0.0'][0]
assert pattern.match(repr(mem_var))
assert mem_var.execution_time == 4
assert mem_var.start_time == 3
diff --git a/test/test_schedule.py b/test/test_schedule.py
index c7305ecb3b17d769ed1ce0b84d2925ca399c962a..088cd60b4c3c5ee88318e595c2062c64b84d6e8b 100644
--- a/test/test_schedule.py
+++ b/test/test_schedule.py
@@ -20,10 +20,10 @@ class TestInit:
schedule = Schedule(sfg_simple_filter)
assert schedule._start_times == {
- "in1": 0,
- "add1": 4,
- "cmul1": 0,
- "out1": 0,
+ "in0": 0,
+ "add0": 4,
+ "cmul0": 0,
+ "out0": 0,
}
assert schedule.schedule_time == 9
@@ -293,19 +293,19 @@ class TestSlacks:
captured = capsys.readouterr()
assert captured.out == """Graph ID | Backward | Forward
---------|----------|---------
+add0 | 0 | 0
add1 | 0 | 0
add2 | 0 | 0
-add3 | 0 | 0
-add4 | 0 | 7
-cmul1 | 0 | 1
+add3 | 0 | 7
+cmul0 | 0 | 1
+cmul1 | 0 | 0
cmul2 | 0 | 0
-cmul3 | 0 | 0
-cmul4 | 4 | 0
+cmul3 | 4 | 0
+cmul4 | 16 | 0
cmul5 | 16 | 0
-cmul6 | 16 | 0
-cmul7 | 4 | 0
-in1 | oo | 0
-out1 | 0 | oo
+cmul6 | 4 | 0
+in0 | oo | 0
+out0 | 0 | oo
"""
assert captured.err == ""
@@ -318,19 +318,19 @@ out1 | 0 | oo
captured = capsys.readouterr()
assert captured.out == """Graph ID | Backward | Forward
---------|----------|---------
-cmul1 | 0 | 1
+cmul0 | 0 | 1
+add0 | 0 | 0
add1 | 0 | 0
-add2 | 0 | 0
+cmul1 | 0 | 0
cmul2 | 0 | 0
-cmul3 | 0 | 0
-add4 | 0 | 7
-add3 | 0 | 0
-out1 | 0 | oo
-cmul4 | 4 | 0
-cmul7 | 4 | 0
+add3 | 0 | 7
+add2 | 0 | 0
+out0 | 0 | oo
+cmul3 | 4 | 0
+cmul6 | 4 | 0
+cmul4 | 16 | 0
cmul5 | 16 | 0
-cmul6 | 16 | 0
-in1 | oo | 0
+in0 | oo | 0
"""
assert captured.err == ""
@@ -420,7 +420,7 @@ class TestRescheduling:
schedule = Schedule(precedence_sfg_delays, algorithm="ASAP")
with pytest.raises(
ValueError,
- match="Operation 'add4' got incorrect move: -4. Must be between 0 and 7.",
+ match="Operation 'add3' got incorrect move: -4. Must be between 0 and 7.",
):
schedule.move_operation(
precedence_sfg_delays.find_by_name("ADD3")[0].graph_id, -4
@@ -433,7 +433,7 @@ class TestRescheduling:
schedule = Schedule(precedence_sfg_delays, algorithm="ASAP")
with pytest.raises(
ValueError,
- match="Operation 'add4' got incorrect move: 10. Must be between 0 and 7.",
+ match="Operation 'add3' got incorrect move: 10. Must be between 0 and 7.",
):
schedule.move_operation(
precedence_sfg_delays.find_by_name("ADD3")[0].graph_id, 10
@@ -444,23 +444,23 @@ class TestRescheduling:
precedence_sfg_delays.set_latency_of_type(ConstantMultiplication.type_name(), 3)
schedule = Schedule(precedence_sfg_delays, algorithm="ASAP")
- assert schedule.backward_slack('cmul6') == 16
- assert schedule.forward_slack('cmul6') == 0
- schedule.move_operation_asap('cmul6')
- assert schedule.start_time_of_operation('in1') == 0
- assert schedule.laps['cmul6'] == 0
- assert schedule.backward_slack('cmul6') == 0
- assert schedule.forward_slack('cmul6') == 16
+ assert schedule.backward_slack('cmul5') == 16
+ assert schedule.forward_slack('cmul5') == 0
+ schedule.move_operation_asap('cmul5')
+ assert schedule.start_time_of_operation('in0') == 0
+ assert schedule.laps['cmul5'] == 0
+ assert schedule.backward_slack('cmul5') == 0
+ assert schedule.forward_slack('cmul5') == 16
def test_move_input_asap_does_not_mess_up_laps(self, precedence_sfg_delays):
precedence_sfg_delays.set_latency_of_type(Addition.type_name(), 1)
precedence_sfg_delays.set_latency_of_type(ConstantMultiplication.type_name(), 3)
schedule = Schedule(precedence_sfg_delays, algorithm="ASAP")
- old_laps = schedule.laps['in1']
- schedule.move_operation_asap('in1')
- assert schedule.start_time_of_operation('in1') == 0
- assert schedule.laps['in1'] == old_laps
+ old_laps = schedule.laps['in0']
+ schedule.move_operation_asap('in0')
+ assert schedule.start_time_of_operation('in0') == 0
+ assert schedule.laps['in0'] == old_laps
def test_move_operation_acc(self):
in0 = Input()
@@ -473,51 +473,51 @@ class TestRescheduling:
schedule = Schedule(sfg, cyclic=True)
# Check initial conditions
- assert schedule.laps[sfg.find_by_id("add1").input(0).signals[0].graph_id] == 1
- assert schedule.laps[sfg.find_by_id("add1").input(1).signals[0].graph_id] == 0
- assert schedule._start_times["add1"] == 0
- assert schedule.laps[sfg.find_by_id("out1").input(0).signals[0].graph_id] == 0
- assert schedule._start_times["out1"] == 1
+ assert schedule.laps[sfg.find_by_id("add0").input(0).signals[0].graph_id] == 1
+ assert schedule.laps[sfg.find_by_id("add0").input(1).signals[0].graph_id] == 0
+ assert schedule._start_times["add0"] == 0
+ assert schedule.laps[sfg.find_by_id("out0").input(0).signals[0].graph_id] == 0
+ assert schedule._start_times["out0"] == 1
# Move and scheduling algorithm behaves differently
- schedule.move_operation("out1", 0)
- assert schedule.laps[sfg.find_by_id("out1").input(0).signals[0].graph_id] == 0
- assert schedule.laps[sfg.find_by_id("add1").input(0).signals[0].graph_id] == 1
- assert schedule.laps[sfg.find_by_id("add1").input(1).signals[0].graph_id] == 0
- assert schedule._start_times["out1"] == 1
- assert schedule._start_times["add1"] == 0
+ schedule.move_operation("out0", 0)
+ assert schedule.laps[sfg.find_by_id("out0").input(0).signals[0].graph_id] == 0
+ assert schedule.laps[sfg.find_by_id("add0").input(0).signals[0].graph_id] == 1
+ assert schedule.laps[sfg.find_by_id("add0").input(1).signals[0].graph_id] == 0
+ assert schedule._start_times["out0"] == 1
+ assert schedule._start_times["add0"] == 0
# Increase schedule time
schedule.set_schedule_time(2)
- assert schedule.laps[sfg.find_by_id("out1").input(0).signals[0].graph_id] == 0
- assert schedule.laps[sfg.find_by_id("add1").input(0).signals[0].graph_id] == 1
- assert schedule.laps[sfg.find_by_id("add1").input(1).signals[0].graph_id] == 0
- assert schedule._start_times["out1"] == 1
- assert schedule._start_times["add1"] == 0
+ assert schedule.laps[sfg.find_by_id("out0").input(0).signals[0].graph_id] == 0
+ assert schedule.laps[sfg.find_by_id("add0").input(0).signals[0].graph_id] == 1
+ assert schedule.laps[sfg.find_by_id("add0").input(1).signals[0].graph_id] == 0
+ assert schedule._start_times["out0"] == 1
+ assert schedule._start_times["add0"] == 0
# Move out one time unit
- schedule.move_operation("out1", 1)
- assert schedule.laps[sfg.find_by_id("out1").input(0).signals[0].graph_id] == 0
- assert schedule.laps[sfg.find_by_id("add1").input(0).signals[0].graph_id] == 1
- assert schedule.laps[sfg.find_by_id("add1").input(1).signals[0].graph_id] == 0
- assert schedule._start_times["out1"] == 2
- assert schedule._start_times["add1"] == 0
+ schedule.move_operation("out0", 1)
+ assert schedule.laps[sfg.find_by_id("out0").input(0).signals[0].graph_id] == 0
+ assert schedule.laps[sfg.find_by_id("add0").input(0).signals[0].graph_id] == 1
+ assert schedule.laps[sfg.find_by_id("add0").input(1).signals[0].graph_id] == 0
+ assert schedule._start_times["out0"] == 2
+ assert schedule._start_times["add0"] == 0
# Move add one time unit
- schedule.move_operation("add1", 1)
- assert schedule.laps[sfg.find_by_id("add1").input(0).signals[0].graph_id] == 1
- assert schedule.laps[sfg.find_by_id("add1").input(1).signals[0].graph_id] == 0
- assert schedule.laps[sfg.find_by_id("out1").input(0).signals[0].graph_id] == 0
- assert schedule._start_times["add1"] == 1
- assert schedule._start_times["out1"] == 2
+ schedule.move_operation("add0", 1)
+ assert schedule.laps[sfg.find_by_id("add0").input(0).signals[0].graph_id] == 1
+ assert schedule.laps[sfg.find_by_id("add0").input(1).signals[0].graph_id] == 0
+ assert schedule.laps[sfg.find_by_id("out0").input(0).signals[0].graph_id] == 0
+ assert schedule._start_times["add0"] == 1
+ assert schedule._start_times["out0"] == 2
# Move add back one time unit
- schedule.move_operation("add1", -1)
- assert schedule.laps[sfg.find_by_id("add1").input(0).signals[0].graph_id] == 1
- assert schedule.laps[sfg.find_by_id("add1").input(1).signals[0].graph_id] == 0
- assert schedule.laps[sfg.find_by_id("out1").input(0).signals[0].graph_id] == 0
- assert schedule._start_times["add1"] == 0
- assert schedule._start_times["out1"] == 2
+ schedule.move_operation("add0", -1)
+ assert schedule.laps[sfg.find_by_id("add0").input(0).signals[0].graph_id] == 1
+ assert schedule.laps[sfg.find_by_id("add0").input(1).signals[0].graph_id] == 0
+ assert schedule.laps[sfg.find_by_id("out0").input(0).signals[0].graph_id] == 0
+ assert schedule._start_times["add0"] == 0
+ assert schedule._start_times["out0"] == 2
class TestTimeResolution:
@@ -673,7 +673,7 @@ class TestErrors:
def test_no_latency(self, sfg_simple_filter):
with pytest.raises(
ValueError,
- match="Input port 0 of operation add1 has no latency-offset.",
+ match="Input port 0 of operation add0 has no latency-offset.",
):
Schedule(sfg_simple_filter)
@@ -686,7 +686,7 @@ class TestErrors:
sfg = SFG([in1, in2], [out1, out2])
with pytest.raises(
ValueError,
- match="Output port 1 of operation bfly1 has no latency-offset.",
+ match="Output port 1 of operation bfly0 has no latency-offset.",
):
Schedule(sfg)
in1 = Input()
@@ -702,7 +702,7 @@ class TestErrors:
sfg = SFG([in1, in2], [out1, out2])
with pytest.raises(
ValueError,
- match="Output port 0 of operation bfly1 has no latency-offset.",
+ match="Output port 0 of operation bfly0 has no latency-offset.",
):
Schedule(sfg)
@@ -764,8 +764,8 @@ class TestYLocations:
# Assign locations
schedule.show()
print(schedule._y_locations)
- assert schedule._y_locations == {'in1': 0, 'cmul1': 1, 'add1': 2, 'out1': 3}
- schedule.move_y_location('add1', 1, insert=True)
- assert schedule._y_locations == {'in1': 0, 'cmul1': 2, 'add1': 1, 'out1': 3}
- schedule.move_y_location('out1', 1)
- assert schedule._y_locations == {'in1': 0, 'cmul1': 2, 'add1': 1, 'out1': 1}
+ assert schedule._y_locations == {'in0': 0, 'cmul0': 1, 'add0': 2, 'out0': 3}
+ schedule.move_y_location('add0', 1, insert=True)
+ assert schedule._y_locations == {'in0': 0, 'cmul0': 2, 'add0': 1, 'out0': 3}
+ schedule.move_y_location('out0', 1)
+ assert schedule._y_locations == {'in0': 0, 'cmul0': 2, 'add0': 1, 'out0': 1}
diff --git a/test/test_sfg.py b/test/test_sfg.py
index 2258081c31bfa03ebf82d50ab27c6781ffa96dc3..df775bc8116cfe50d08787b68b463233e338fc4c 100644
--- a/test/test_sfg.py
+++ b/test/test_sfg.py
@@ -303,7 +303,7 @@ class TestComponents:
class TestReplaceOperation:
def test_replace_addition_by_id(self, operation_tree):
sfg = SFG(outputs=[Output(operation_tree)])
- component_id = "add1"
+ component_id = "add0"
sfg = sfg.replace_operation(Multiplication(name="Multi"), graph_id=component_id)
assert component_id not in sfg._components_by_id.keys()
@@ -311,7 +311,7 @@ class TestReplaceOperation:
def test_replace_addition_large_tree(self, large_operation_tree):
sfg = SFG(outputs=[Output(large_operation_tree)])
- component_id = "add3"
+ component_id = "add2"
sfg = sfg.replace_operation(Multiplication(name="Multi"), graph_id=component_id)
assert "Multi" in sfg._components_by_name.keys()
@@ -319,7 +319,7 @@ class TestReplaceOperation:
def test_replace_no_input_component(self, operation_tree):
sfg = SFG(outputs=[Output(operation_tree)])
- component_id = "c1"
+ component_id = "c0"
const_ = sfg.find_by_id(component_id)
sfg = sfg.replace_operation(Constant(1), graph_id=component_id)
@@ -327,7 +327,7 @@ class TestReplaceOperation:
def test_no_match_on_replace(self, large_operation_tree):
sfg = SFG(outputs=[Output(large_operation_tree)])
- component_id = "addd1"
+ component_id = "addd0"
with pytest.raises(
ValueError, match="No operation matching the criteria found"
@@ -338,7 +338,7 @@ class TestReplaceOperation:
def test_not_equal_input(self, large_operation_tree):
sfg = SFG(outputs=[Output(large_operation_tree)])
- component_id = "c1"
+ component_id = "c0"
with pytest.raises(
TypeError,
@@ -374,13 +374,13 @@ class TestInsertComponent:
assert sfg.find_by_name("constant4")[0].output(0).signals[
0
- ].destination.operation is sfg.find_by_id("add3")
+ ].destination.operation is sfg.find_by_id("add2")
assert _sfg.find_by_name("constant4")[0].output(0).signals[
0
- ].destination.operation is not _sfg.find_by_id("add3")
- assert _sfg.find_by_id("sqrt1").output(0).signals[
+ ].destination.operation is not _sfg.find_by_id("add2")
+ assert _sfg.find_by_id("sqrt0").output(0).signals[
0
- ].destination.operation is _sfg.find_by_id("add3")
+ ].destination.operation is _sfg.find_by_id("add2")
def test_insert_invalid_component_in_sfg(self, large_operation_tree):
sfg = SFG(outputs=[Output(large_operation_tree)])
@@ -388,7 +388,7 @@ class TestInsertComponent:
# Should raise an exception for not matching input count to output count.
add4 = Addition()
with pytest.raises(TypeError, match="Source operation output count"):
- sfg.insert_operation(add4, "c1")
+ sfg.insert_operation(add4, "c0")
def test_insert_at_output(self, large_operation_tree):
sfg = SFG(outputs=[Output(large_operation_tree)])
@@ -396,11 +396,11 @@ class TestInsertComponent:
# Should raise an exception for trying to insert an operation after an output.
sqrt = SquareRoot()
with pytest.raises(TypeError, match="Source operation cannot be an"):
- _ = sfg.insert_operation(sqrt, "out1")
+ _ = sfg.insert_operation(sqrt, "out0")
def test_insert_multiple_output_ports(self, butterfly_operation_tree):
sfg = SFG(outputs=list(map(Output, butterfly_operation_tree.outputs)))
- _sfg = sfg.insert_operation(Butterfly(name="n_bfly"), "bfly3")
+ _sfg = sfg.insert_operation(Butterfly(name="n_bfly"), "bfly2")
assert sfg.evaluate() != _sfg.evaluate()
@@ -987,7 +987,7 @@ class TestTopologicalOrderOperations:
class TestRemove:
def test_remove_single_input_outputs(self, sfg_simple_filter):
- new_sfg = sfg_simple_filter.remove_operation("cmul1")
+ new_sfg = sfg_simple_filter.remove_operation("cmul0")
assert {
op.name
@@ -1181,19 +1181,19 @@ class TestGetComponentsOfType:
class TestPrecedenceGraph:
def test_precedence_graph(self, sfg_simple_filter):
res = (
- 'digraph {\n\trankdir=LR\n\tsubgraph cluster_0 {\n\t\tlabel=N0\n\t\t"in1.0"'
- ' [label=in1 height=0.1 shape=rectangle width=0.1]\n\t\t"t1.0" [label=t1'
+ 'digraph {\n\trankdir=LR\n\tsubgraph cluster_0 {\n\t\tlabel=N0\n\t\t"in0.0"'
+ ' [label=in0 height=0.1 shape=rectangle width=0.1]\n\t\t"t0.0" [label=t0'
' height=0.1 shape=rectangle width=0.1]\n\t}\n\tsubgraph cluster_1'
- ' {\n\t\tlabel=N1\n\t\t"cmul1.0" [label=cmul1 height=0.1 shape=rectangle'
- ' width=0.1]\n\t}\n\tsubgraph cluster_2 {\n\t\tlabel=N2\n\t\t"add1.0"'
- ' [label=add1 height=0.1 shape=rectangle width=0.1]\n\t}\n\t"in1.0" ->'
- ' add1\n\tadd1 [label=add1 shape=ellipse]\n\tin1 -> "in1.0"\n\tin1'
- ' [label=in1 shape=cds]\n\t"t1.0" -> cmul1\n\tcmul1 [label=cmul1'
- ' shape=ellipse]\n\t"t1.0" -> out1\n\tout1 [label=out1 shape=cds]\n\tt1Out'
- ' -> "t1.0"\n\tt1Out [label=t1 shape=square]\n\t"cmul1.0" -> add1\n\tadd1'
- ' [label=add1 shape=ellipse]\n\tcmul1 -> "cmul1.0"\n\tcmul1 [label=cmul1'
- ' shape=ellipse]\n\t"add1.0" -> t1In\n\tt1In [label=t1'
- ' shape=square]\n\tadd1 -> "add1.0"\n\tadd1 [label=add1 shape=ellipse]\n}'
+ ' {\n\t\tlabel=N1\n\t\t"cmul0.0" [label=cmul0 height=0.1 shape=rectangle'
+ ' width=0.1]\n\t}\n\tsubgraph cluster_2 {\n\t\tlabel=N2\n\t\t"add0.0"'
+ ' [label=add0 height=0.1 shape=rectangle width=0.1]\n\t}\n\t"in0.0" ->'
+ ' add0\n\tadd0 [label=add0 shape=ellipse]\n\tin0 -> "in0.0"\n\tin0'
+ ' [label=in0 shape=cds]\n\t"t0.0" -> cmul0\n\tcmul0 [label=cmul0'
+ ' shape=ellipse]\n\t"t0.0" -> out0\n\tout0 [label=out0 shape=cds]\n\tt0Out'
+ ' -> "t0.0"\n\tt0Out [label=t0 shape=square]\n\t"cmul0.0" -> add0\n\tadd0'
+ ' [label=add0 shape=ellipse]\n\tcmul0 -> "cmul0.0"\n\tcmul0 [label=cmul0'
+ ' shape=ellipse]\n\t"add0.0" -> t0In\n\tt0In [label=t0'
+ ' shape=square]\n\tadd0 -> "add0.0"\n\tadd0 [label=add0 shape=ellipse]\n}'
)
assert sfg_simple_filter.precedence_graph.source in (res, res + "\n")
@@ -1202,10 +1202,10 @@ class TestPrecedenceGraph:
class TestSFGGraph:
def test_sfg(self, sfg_simple_filter):
res = (
- 'digraph {\n\trankdir=LR splines=spline\n\tin1 [shape=cds]\n\tin1 -> add1'
- ' [headlabel=0]\n\tout1 [shape=cds]\n\tt1 -> out1\n\tadd1'
- ' [shape=ellipse]\n\tcmul1 -> add1 [headlabel=1]\n\tcmul1'
- ' [shape=ellipse]\n\tadd1 -> t1\n\tt1 [shape=square]\n\tt1 -> cmul1\n}'
+ 'digraph {\n\trankdir=LR splines=spline\n\tin0 [shape=cds]\n\tin0 -> add0'
+ ' [headlabel=0]\n\tout0 [shape=cds]\n\tt0 -> out0\n\tadd0'
+ ' [shape=ellipse]\n\tcmul0 -> add0 [headlabel=1]\n\tcmul0'
+ ' [shape=ellipse]\n\tadd0 -> t0\n\tt0 [shape=square]\n\tt0 -> cmul0\n}'
)
assert sfg_simple_filter.sfg_digraph(branch_node=False).source in (
res,
@@ -1214,11 +1214,11 @@ class TestSFGGraph:
def test_sfg_show_id(self, sfg_simple_filter):
res = (
- 'digraph {\n\trankdir=LR splines=spline\n\tin1 [shape=cds]\n\tin1 -> add1'
- ' [label=s1 headlabel=0]\n\tout1 [shape=cds]\n\tt1 -> out1'
- ' [label=s2]\n\tadd1 [shape=ellipse]\n\tcmul1 -> add1 [label=s3'
- ' headlabel=1]\n\tcmul1 [shape=ellipse]\n\tadd1 -> t1 [label=s4]\n\tt1'
- ' [shape=square]\n\tt1 -> cmul1 [label=s5]\n}'
+ 'digraph {\n\trankdir=LR splines=spline\n\tin0 [shape=cds]\n\tin0 -> add0'
+ ' [label=s0 headlabel=0]\n\tout0 [shape=cds]\n\tt0 -> out0'
+ ' [label=s1]\n\tadd0 [shape=ellipse]\n\tcmul0 -> add0 [label=s2'
+ ' headlabel=1]\n\tcmul0 [shape=ellipse]\n\tadd0 -> t0 [label=s3]\n\tt0'
+ ' [shape=square]\n\tt0 -> cmul0 [label=s4]\n}'
)
assert sfg_simple_filter.sfg_digraph(
@@ -1230,12 +1230,12 @@ class TestSFGGraph:
def test_sfg_branch(self, sfg_simple_filter):
res = (
- 'digraph {\n\trankdir=LR splines=spline\n\tin1 [shape=cds]\n\tin1 -> add1'
- ' [headlabel=0]\n\tout1 [shape=cds]\n\t"t1.0" -> out1\n\t"t1.0"'
- ' [shape=point]\n\tt1 -> "t1.0" [arrowhead=none]\n\tadd1'
- ' [shape=ellipse]\n\tcmul1 -> add1 [headlabel=1]\n\tcmul1'
- ' [shape=ellipse]\n\tadd1 -> t1\n\tt1 [shape=square]\n\t"t1.0" ->'
- ' cmul1\n}'
+ 'digraph {\n\trankdir=LR splines=spline\n\tin0 [shape=cds]\n\tin0 -> add0'
+ ' [headlabel=0]\n\tout0 [shape=cds]\n\t"t0.0" -> out0\n\t"t0.0"'
+ ' [shape=point]\n\tt0 -> "t0.0" [arrowhead=none]\n\tadd0'
+ ' [shape=ellipse]\n\tcmul0 -> add0 [headlabel=1]\n\tcmul0'
+ ' [shape=ellipse]\n\tadd0 -> t0\n\tt0 [shape=square]\n\t"t0.0" ->'
+ ' cmul0\n}'
)
assert sfg_simple_filter.sfg_digraph().source in (
@@ -1245,10 +1245,10 @@ class TestSFGGraph:
def test_sfg_no_port_numbering(self, sfg_simple_filter):
res = (
- 'digraph {\n\trankdir=LR splines=spline\n\tin1 [shape=cds]\n\tin1 ->'
- ' add1\n\tout1 [shape=cds]\n\tt1 -> out1\n\tadd1 [shape=ellipse]\n\tcmul1'
- ' -> add1\n\tcmul1 [shape=ellipse]\n\tadd1 -> t1\n\tt1 [shape=square]\n\tt1'
- ' -> cmul1\n}'
+ 'digraph {\n\trankdir=LR splines=spline\n\tin0 [shape=cds]\n\tin0 ->'
+ ' add0\n\tout0 [shape=cds]\n\tt0 -> out0\n\tadd0 [shape=ellipse]\n\tcmul0'
+ ' -> add0\n\tcmul0 [shape=ellipse]\n\tadd0 -> t0\n\tt0 [shape=square]\n\tt0'
+ ' -> cmul0\n}'
)
assert sfg_simple_filter.sfg_digraph(
@@ -1384,7 +1384,7 @@ class TestSFGErrors:
ValueError,
match="Different number of input and output ports of operation with",
):
- sfg.remove_operation('add1')
+ sfg.remove_operation('add0')
def test_inputs_required_for_output(self):
in1 = Input()
@@ -1591,13 +1591,13 @@ class TestInsertComponentAfter:
assert sfg.find_by_name("constant4")[0].output(0).signals[
0
- ].destination.operation is sfg.find_by_id("add3")
+ ].destination.operation is sfg.find_by_id("add2")
assert _sfg.find_by_name("constant4")[0].output(0).signals[
0
- ].destination.operation is not _sfg.find_by_id("add3")
- assert _sfg.find_by_id("sqrt1").output(0).signals[
+ ].destination.operation is not _sfg.find_by_id("add2")
+ assert _sfg.find_by_id("sqrt0").output(0).signals[
0
- ].destination.operation is _sfg.find_by_id("add3")
+ ].destination.operation is _sfg.find_by_id("add2")
def test_insert_component_after_mimo_operation_error(
self, large_operation_tree_names
diff --git a/test/test_simulation.py b/test/test_simulation.py
index cdcb86c0c82e1a6c6a2b5f0a603ef101ad086a5d..aa9340a222ee2fea1586baaefb167cd35c0c26f5 100644
--- a/test/test_simulation.py
+++ b/test/test_simulation.py
@@ -18,31 +18,31 @@ class TestRunFor:
assert simulation.results["0"][100] == 304
assert simulation.results["1"][100] == 505
- assert simulation.results["in1"][0] == 3
- assert simulation.results["in2"][0] == 1
- assert simulation.results["add1"][0] == 4
- assert simulation.results["add2"][0] == 5
+ assert simulation.results["in0"][0] == 3
+ assert simulation.results["in1"][0] == 1
+ assert simulation.results["add0"][0] == 4
+ assert simulation.results["add1"][0] == 5
assert simulation.results["0"][0] == 4
assert simulation.results["1"][0] == 5
- assert simulation.results["in1"][1] == 4
- assert simulation.results["in2"][1] == 3
- assert simulation.results["add1"][1] == 7
- assert simulation.results["add2"][1] == 10
+ assert simulation.results["in0"][1] == 4
+ assert simulation.results["in1"][1] == 3
+ assert simulation.results["add0"][1] == 7
+ assert simulation.results["add1"][1] == 10
assert simulation.results["0"][1] == 7
assert simulation.results["1"][1] == 10
+ assert simulation.results["in0"][2] == 5
assert simulation.results["in1"][2] == 5
- assert simulation.results["in2"][2] == 5
- assert simulation.results["add1"][2] == 10
- assert simulation.results["add2"][2] == 15
+ assert simulation.results["add0"][2] == 10
+ assert simulation.results["add1"][2] == 15
assert simulation.results["0"][2] == 10
assert simulation.results["1"][2] == 15
- assert simulation.results["in1"][3] == 6
- assert simulation.results["in2"][3] == 7
- assert simulation.results["add1"][3] == 13
- assert simulation.results["add2"][3] == 20
+ assert simulation.results["in0"][3] == 6
+ assert simulation.results["in1"][3] == 7
+ assert simulation.results["add0"][3] == 13
+ assert simulation.results["add1"][3] == 20
assert simulation.results["0"][3] == 13
assert simulation.results["1"][3] == 20
@@ -58,38 +58,38 @@ class TestRunFor:
assert output[0] == 9
assert output[1] == 11
+ assert isinstance(simulation.results["in0"], np.ndarray)
assert isinstance(simulation.results["in1"], np.ndarray)
- assert isinstance(simulation.results["in2"], np.ndarray)
+ assert isinstance(simulation.results["add0"], np.ndarray)
assert isinstance(simulation.results["add1"], np.ndarray)
- assert isinstance(simulation.results["add2"], np.ndarray)
assert isinstance(simulation.results["0"], np.ndarray)
assert isinstance(simulation.results["1"], np.ndarray)
- assert simulation.results["in1"][0] == 5
- assert simulation.results["in2"][0] == 7
- assert simulation.results["add1"][0] == 12
- assert simulation.results["add2"][0] == 19
+ assert simulation.results["in0"][0] == 5
+ assert simulation.results["in1"][0] == 7
+ assert simulation.results["add0"][0] == 12
+ assert simulation.results["add1"][0] == 19
assert simulation.results["0"][0] == 12
assert simulation.results["1"][0] == 19
- assert simulation.results["in1"][1] == 9
- assert simulation.results["in2"][1] == 3
- assert simulation.results["add1"][1] == 12
- assert simulation.results["add2"][1] == 15
+ assert simulation.results["in0"][1] == 9
+ assert simulation.results["in1"][1] == 3
+ assert simulation.results["add0"][1] == 12
+ assert simulation.results["add1"][1] == 15
assert simulation.results["0"][1] == 12
assert simulation.results["1"][1] == 15
- assert simulation.results["in1"][2] == 25
- assert simulation.results["in2"][2] == 3
- assert simulation.results["add1"][2] == 28
- assert simulation.results["add2"][2] == 31
+ assert simulation.results["in0"][2] == 25
+ assert simulation.results["in1"][2] == 3
+ assert simulation.results["add0"][2] == 28
+ assert simulation.results["add1"][2] == 31
assert simulation.results["0"][2] == 28
assert simulation.results["1"][2] == 31
- assert simulation.results["in1"][3] == -5
- assert simulation.results["in2"][3] == 54
- assert simulation.results["add1"][3] == 49
- assert simulation.results["add2"][3] == 103
+ assert simulation.results["in0"][3] == -5
+ assert simulation.results["in1"][3] == 54
+ assert simulation.results["add0"][3] == 49
+ assert simulation.results["add1"][3] == 103
assert simulation.results["0"][3] == 49
assert simulation.results["1"][3] == 103