diff --git a/test/signal/test_signal.py b/test/signal/test_signal.py
index c4cf0390fc53f19d29b7399650698d384dad9e24..8c10d1e36fcb292ab8bfc7d10843edf9ca475135 100644
--- a/test/signal/test_signal.py
+++ b/test/signal/test_signal.py
@@ -1,9 +1,13 @@
+"""
+B-ASIC test suit for the signal module which consists of the Signal class.
+"""
+
 from b_asic.port import InputPort, OutputPort
 from b_asic.signal import Signal
 
 import pytest
 
-def test_explicit_signal_creation():
+def test_signal_creation_and_disconnction_and_connection_changing():
     in_port = InputPort(0, None)
     out_port = OutputPort(1, None)
     s = Signal(out_port, in_port)
@@ -13,10 +17,46 @@ def test_explicit_signal_creation():
     assert s.source is out_port
     assert s.destination is in_port
 
-def test_implicit_signal_creation():
-    in_port = InputPort(0, None)
-    out_port = OutputPort(1, None)
-    s = in_port.connect_port(out_port)
+    in_port1 = InputPort(0, None)
+    s.connect_destination(in_port1)
+
+    assert in_port.signals == []
+    assert in_port1.signals == [s]
+    assert out_port.signals == [s]
+    assert s.source is out_port
+    assert s.destination is in_port1
+
+    s.disconnect_source()
+
+    assert out_port.signals == []
+    assert in_port1.signals == [s]
+    assert s.source is None
+    assert s.destination is in_port1
+
+    s.disconnect_destination()
+
+    assert out_port.signals == []
+    assert in_port1.signals == []
+    assert s.source is None
+    assert s.destination is None
 
+    out_port1 = OutputPort(0, None)
+    s.connect_source(out_port1)
+
+    assert out_port1.signals == [s]
+    assert s.source is out_port1
+    assert s.destination is None
+
+    s.connect_source(out_port)
+
+    assert out_port.signals == [s]
+    assert out_port1.signals == []
+    assert s.source is out_port
+    assert s.destination is None
+
+    s.connect_destination(in_port)
+
+    assert out_port.signals == [s]
     assert in_port.signals == [s]
-    assert out_port.signals == [s]
\ No newline at end of file
+    assert s.source is out_port
+    assert s.destination is in_port