diff --git a/examples/fivepointwinograddft.py b/examples/fivepointwinograddft.py
index f9afd0e6acf5f1a6feeb78449a231832c96e06ab..d21561511d5fafa2c9249adf4ffac5e939e91cd4 100644
--- a/examples/fivepointwinograddft.py
+++ b/examples/fivepointwinograddft.py
@@ -14,6 +14,7 @@ import networkx as nx
 from b_asic.architecture import Architecture, Memory, ProcessingElement
 from b_asic.core_operations import AddSub, Butterfly, ConstantMultiplication
 from b_asic.schedule import Schedule
+from b_asic.scheduler import ASAPScheduler
 from b_asic.signal_flow_graph import SFG
 from b_asic.special_operations import Input, Output
 
@@ -75,7 +76,7 @@ sfg.set_execution_time_of_type(Butterfly.type_name(), 1)
 
 # %%
 # Generate schedule
-schedule = Schedule(sfg, cyclic=True)
+schedule = Schedule(sfg, scheduler=ASAPScheduler(), cyclic=True)
 schedule.show()
 
 # %%
diff --git a/examples/folding_example_with_architecture.py b/examples/folding_example_with_architecture.py
index 9baf92e0162d91167012b10314815f5e9312125b..43bdc798e0a24fcd0ce8a10e66cc27c412b0acea 100644
--- a/examples/folding_example_with_architecture.py
+++ b/examples/folding_example_with_architecture.py
@@ -17,6 +17,7 @@ shorter than the scheduling period.
 from b_asic.architecture import Architecture, Memory, ProcessingElement
 from b_asic.core_operations import Addition, ConstantMultiplication
 from b_asic.schedule import Schedule
+from b_asic.scheduler import ASAPScheduler
 from b_asic.signal_flow_graph import SFG
 from b_asic.special_operations import Delay, Input, Output
 
@@ -48,7 +49,7 @@ sfg.set_execution_time_of_type(Addition.type_name(), 1)
 
 # %%
 # Create schedule
-schedule = Schedule(sfg, cyclic=True)
+schedule = Schedule(sfg, scheduler=ASAPScheduler(), cyclic=True)
 schedule.show(title='Original schedule')
 
 # %%
diff --git a/examples/lwdfallpass.py b/examples/lwdfallpass.py
index 281856fe347c4ec0307d2d96ca78303db1ba7e0b..6bbde6291eca6404efb3a5df66e28633b3ea0a91 100644
--- a/examples/lwdfallpass.py
+++ b/examples/lwdfallpass.py
@@ -9,6 +9,7 @@ This has different latency offsets for the different inputs/outputs.
 
 from b_asic.core_operations import SymmetricTwoportAdaptor
 from b_asic.schedule import Schedule
+from b_asic.scheduler import ASAPScheduler
 from b_asic.signal_flow_graph import SFG
 from b_asic.special_operations import Delay, Input, Output
 
@@ -22,5 +23,5 @@ d0 <<= adaptor0.output(1)
 out0 = Output(adaptor0.output(0))
 adaptor0.execution_time = 2
 sfg = SFG([in0], [out0])
-schedule = Schedule(sfg)
+schedule = Schedule(sfg, scheduler=ASAPScheduler())
 schedule.show()
diff --git a/examples/secondorderdirectformiir.py b/examples/secondorderdirectformiir.py
index b4eee8255a65c8ad0b5ff8e268e1fa186863c4f3..aa84c26b532b0304fd012805bb88b1719723e9a7 100644
--- a/examples/secondorderdirectformiir.py
+++ b/examples/secondorderdirectformiir.py
@@ -7,6 +7,7 @@ Second-order IIR Filter with Schedule
 
 from b_asic.core_operations import Addition, ConstantMultiplication
 from b_asic.schedule import Schedule
+from b_asic.scheduler import ASAPScheduler
 from b_asic.signal_flow_graph import SFG
 from b_asic.special_operations import Delay, Input, Output
 
@@ -43,5 +44,5 @@ sfg.set_execution_time_of_type(Addition.type_name(), 1)
 # %%
 # Create schedule
 
-schedule = Schedule(sfg, cyclic=True)
+schedule = Schedule(sfg, scheduler=ASAPScheduler(), cyclic=True)
 schedule.show()
diff --git a/examples/secondorderdirectformiir_architecture.py b/examples/secondorderdirectformiir_architecture.py
index 1a234a36b5f1b5bbe12deeaebc7c7eb3b3c065e5..a7d72fb36fa631c7a39395597351a9b4c1674930 100644
--- a/examples/secondorderdirectformiir_architecture.py
+++ b/examples/secondorderdirectformiir_architecture.py
@@ -8,6 +8,7 @@ Second-order IIR Filter with Architecture
 from b_asic.architecture import Architecture, Memory, ProcessingElement
 from b_asic.core_operations import Addition, ConstantMultiplication
 from b_asic.schedule import Schedule
+from b_asic.scheduler import ASAPScheduler
 from b_asic.signal_flow_graph import SFG
 from b_asic.special_operations import Delay, Input, Output
 
@@ -42,7 +43,7 @@ sfg.set_execution_time_of_type(Addition.type_name(), 1)
 
 # %%
 # Create schedule.
-schedule = Schedule(sfg, cyclic=True)
+schedule = Schedule(sfg, scheduler=ASAPScheduler(), cyclic=True)
 schedule.show(title='Original schedule')
 
 # %%
diff --git a/examples/thirdorderblwdf.py b/examples/thirdorderblwdf.py
index 7496b07803e6018ae252f7af14dcda9796b84de0..d29fd21566982464ffae9107ba64e79eccf79fce 100644
--- a/examples/thirdorderblwdf.py
+++ b/examples/thirdorderblwdf.py
@@ -11,6 +11,7 @@ from mplsignal.freq_plots import freqz_fir
 
 from b_asic.core_operations import Addition, SymmetricTwoportAdaptor
 from b_asic.schedule import Schedule
+from b_asic.scheduler import ASAPScheduler
 from b_asic.signal_flow_graph import SFG
 from b_asic.signal_generator import Impulse
 from b_asic.simulation import Simulation
@@ -49,5 +50,5 @@ freqz_fir(np.array(sim.results['0']) / 2)
 
 # %%
 # Create and display schedule
-schedule = Schedule(sfg, cyclic=True)
+schedule = Schedule(sfg, scheduler=ASAPScheduler(), cyclic=True)
 schedule.show()
diff --git a/examples/threepointwinograddft.py b/examples/threepointwinograddft.py
index 79bb7fb9037f737a42a6d26ce69672301392c560..7e7a58acd5465969142aa85f95883998b0a74689 100644
--- a/examples/threepointwinograddft.py
+++ b/examples/threepointwinograddft.py
@@ -12,6 +12,7 @@ import networkx as nx
 from b_asic.architecture import Architecture, Memory, ProcessingElement
 from b_asic.core_operations import AddSub, ConstantMultiplication
 from b_asic.schedule import Schedule
+from b_asic.scheduler import ASAPScheduler
 from b_asic.signal_flow_graph import SFG
 from b_asic.special_operations import Input, Output
 
@@ -54,7 +55,7 @@ sfg.set_execution_time_of_type(AddSub.type_name(), 1)
 
 # %%
 # Generate schedule
-schedule = Schedule(sfg, cyclic=True)
+schedule = Schedule(sfg, scheduler=ASAPScheduler(), cyclic=True)
 schedule.show()
 
 # %%